Linear Technology LTC2654-L16 Quad SPI 16-bit Voltage Output DAC with 1.25V Reference, req DC590 DC1678A-A DC1678A-A Data Sheet
Product codes
DC1678A-A
LTC2654
14
2654f
PIN FUNCTIONS
V
OUTA
to V
OUTD
(Pins 1, 3, 13, 14/Pins 2,4,13,14): DAC
Analog Voltage Outputs. The output range is 0V to 2 times
the voltage at the REFIN/OUT pin.
the voltage at the REFIN/OUT pin.
REFCOMP (Pin 2/Pin 3): Internal Reference Compensa-
tion pin. For low noise and reference stability, tie a 0.1μF
capacitor to GND. Connecting this pin to GND allows the
use of external reference at start-up.
tion pin. For low noise and reference stability, tie a 0.1μF
capacitor to GND. Connecting this pin to GND allows the
use of external reference at start-up.
REFIN/OUT (Pin 4/Pin 5): Reference Input/Output. This
pin acts as the internal reference output in internal refer-
ence mode and acts as the reference input pin in external
reference mode. When acting as an output the nominal
voltage at this pin is 1.25V for -L options and 2.048V
for -H options. For low noise and reference stability tie
a capacitor to GND. Capacitor value must be ≤C
pin acts as the internal reference output in internal refer-
ence mode and acts as the reference input pin in external
reference mode. When acting as an output the nominal
voltage at this pin is 1.25V for -L options and 2.048V
for -H options. For low noise and reference stability tie
a capacitor to GND. Capacitor value must be ≤C
REFCOMP
.
In external reference mode, the allowable reference input
voltage range is 0.5V to V
voltage range is 0.5V to V
CC
/2.
LDAC (Pin 5/Pin 6): Asynchronous DAC Update Pin. If
CS/LD is high, a falling edge on LDAC immediately updates
the DAC register with the contents of the input register
(similar to a software update). If CS/LD is low when LDAC
goes low, the DAC register is updated after CS/LD returns
high. A low on the LDAC pin powers up the DAC outputs.
All the software power-down commands are ignored if
the DAC register with the contents of the input register
(similar to a software update). If CS/LD is low when LDAC
goes low, the DAC register is updated after CS/LD returns
high. A low on the LDAC pin powers up the DAC outputs.
All the software power-down commands are ignored if
LDAC is low when CS/LD goes high.
CS/LD (Pin 6/Pin 7): Serial Interface Chip Select/Load
Input. When CS/LD is low, SCK is enabled for shifting
data on SDI into the register. When CS/LD is taken high,
SCK is disabled and the specifi ed command (see Table 1)
is executed.
CS/LD (Pin 6/Pin 7): Serial Interface Chip Select/Load
Input. When CS/LD is low, SCK is enabled for shifting
data on SDI into the register. When CS/LD is taken high,
SCK is disabled and the specifi ed command (see Table 1)
is executed.
SCK (Pin 7/Pin 8): Serial Interface Clock Input. CMOS
and TTL compatible.
and TTL compatible.
DNC (Pins 8, 15, 16, 17/NA): Do not connect these pins.
SDI (Pin 9/Pin 9): Serial Interface Data Input. Data is ap-
plied to SDI for transfer to the device at the rising edge of
SCK (Pin 10). The LTC2654 accepts input word lengths of
either 24 or 32 bits. See Figures 2a and 2b.
plied to SDI for transfer to the device at the rising edge of
SCK (Pin 10). The LTC2654 accepts input word lengths of
either 24 or 32 bits. See Figures 2a and 2b.
SDO (Pin 10/Pin 10): Serial Interface Data Output. This pin
is used for daisy-chain operation. The serial output of the
shift register appears at the SDO pin. The data transferred
to the device via the SDI pin is delayed 32 SCK rising edges
before being output at the next falling edge. This pin is
continuously driven and does not go high impedance when
is used for daisy-chain operation. The serial output of the
shift register appears at the SDO pin. The data transferred
to the device via the SDI pin is delayed 32 SCK rising edges
before being output at the next falling edge. This pin is
continuously driven and does not go high impedance when
CS/LD is taken active high.
CLR (Pin 11/Pin 11): Asynchronous Clear Input. A logic
low at this level-triggered input clears all registers and
causes the DAC voltage outputs to drop to 0V if PORSEL
pin is tied to GND. If the PORSEL pin is tied to V
CLR (Pin 11/Pin 11): Asynchronous Clear Input. A logic
low at this level-triggered input clears all registers and
causes the DAC voltage outputs to drop to 0V if PORSEL
pin is tied to GND. If the PORSEL pin is tied to V
CC
, a logic
low at CLR sets all registers to mid-scale code and causes
the DAC voltage outputs to go to mid-scale.
the DAC voltage outputs to go to mid-scale.
PORSEL (Pin 12/Pin 12): Power-On-Reset Select Pin. If
tied to GND, the DACs reset to zero-scale. If tied to V
tied to GND, the DACs reset to zero-scale. If tied to V
CC
,
the DACs reset to mid-scale.
V
CC
(Pin 18/Pin 15): Supply Voltage Input. For -L op-
tions, 2.7V ≤ V
CC
≤ 5.5V, and for -H options, 4.5V ≤ V
CC
≤ 5.5V. Should be bypassed by a 0.1μF low ESR ceramic
capacitor to GND.
capacitor to GND.
GND (Pin 19, Exposed Pad Pin 21/Pin 16): Ground.
Exposed pad must be soldered to PCB Ground.
Exposed pad must be soldered to PCB Ground.
REFLO (Pin 20/Pin 1): Reference Low Pin. The voltage at
this pin sets the zero-scale voltage of all DACs. This pin
should be tied to GND.
this pin sets the zero-scale voltage of all DACs. This pin
should be tied to GND.
(QFN/SSOP)