Mikroelektronika MikroE Development Kits MIKROE-996 Data Sheet

DS39960D-page 174

 2009-2011 Microchip Technology Inc.

PORTC is an eight-bit wide, bidirectional port. The
corresponding Data Direction and Output Latch registers
are TRISC and LATC. Only PORTC pins, RC2 through
RC7, are digital only pins.
PORTC is multiplexed with ECCP, MSSP and EUSART
peripheral functions (

). The pins have

Schmitt Trigger input buffers. The pins for ECCP, SPI
and EUSART are also configurable for open-drain out-
put whenever these functions are active. Open-drain
configuration is selected by setting the SPIOD,
CCPxOD and U1OD control bits in the registers,
ODCON1 and ODCON3.
RC1 is normally configured as the default peripheral
pin for the ECCP2 module. The assignment of ECCP2
is controlled by Configuration bit, CCP2MX (default
state, CCP2MX = 1). 

When enabling peripheral functions, use care in defin-
ing TRIS bits for each PORTC pin. Some peripherals
can override the TRIS bit to make a pin an output or
input. Consult the corresponding peripheral section for
the correct TRIS bit settings.

The contents of the TRISC register are affected by
peripheral overrides. Reading TRISC always returns
the current contents, even though a peripheral device
may be overriding one or more of the pins.

These pins are configured as digital inputs
on any device Reset.

CLRF

PORTC

;

  Initialize PORTC by

; clearing output

; data latches

CLRF

LATC

; Alternate method

; to clear output

; data latches

MOVLW

0CFh

;

  Value used to 

; initialize data       

             

; direction

MOVWF

TRISC

;

  Set RC<3:0> as inputs

; RC<5:4> as outputs

;

  RC<7:6> as inputs

RC0/SOSCO/
SCLKI/

RC0

0

O

DIG

LATC<0> data output.

1

I

ST

PORTC<0> data input.

SOSCO

1

I

ST

SOSC oscillator output.

SCLKI

1

I

ST

Digital clock input; enabled when SOSC oscillator is disabled.

RC1/SOSCI/
ECCP2/P2A

RC1

0

O

DIG

LATC<1> data output.

1

I

ST

PORTC<1> data input.

SOSCI

x

I

ANA

SOSC oscillator input.

ECCP2

0

O

DIG

ECCP2 compare output and ECCP2 PWM output; takes priority over port data.

1

I

ST

ECCP2 capture input.

P2A

0

O

DIG

ECCP2 Enhanced PWM output, Channel A.
May be configured for tri-state during Enhanced PWM shutdown events; takes 
priority over port data.

RC2/ECCP1/
P1A

RC2

0

O

DIG

LATC<2> data output.

1

I

ST

PORTC<2> data input.

ECCP1

0

O

DIG

ECCP1 compare output and ECCP1 PWM output; takes priority over port data.

1

I

ST

ECCP1 capture input.

P1A

0

O

DIG

ECCP1 Enhanced PWM output, Channel A.
May be configured for tri-state during Enhanced PWM shutdown events; takes 
priority over port data.

O = Output, I = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Trigger Buffer Input, TTL = TTL Buffer Input, 
I

2

C = I

2

C™/SMBus Buffer Input, x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).

Default assignment for ECCP2 when the CCP2MX Configuration bit is set.