Mikroelektronika MikroE Development Kits MIKROE-996 Data Sheet
Product codes
MIKROE-996
2009-2011 Microchip Technology Inc.
DS39960D-page 179
PIC18F87K22 FAMILY
RE2/CS/P2B/
CCP10/AD10
CCP10/AD10
RE2
0
O
DIG
LATE<2> data output.
1
I
ST
PORTE<2> data input.
CS
x
I
TTL
Parallel Slave Port chip select.
P2B
0
O
—
ECCP2 PWM Output B.
May be configured for tri-state during Enhanced PWM shutdown events.
May be configured for tri-state during Enhanced PWM shutdown events.
CCP10
1
I/O
ST
Capture 10 input/Compare 10 output/PWM10 output.
AD10
x
O
DIG
External memory interface, Address/Data Bit 10 output.
x
I
TTL
External memory interface, Data Bit 10 input.
RE3/P3C/
CCP9/REFO/
AD11
CCP9/REFO/
AD11
RE3
0
O
DIG
LATE<3> data output.
1
I
ST
PORTE<3> data input.
P3C
0
O
—
ECCP3 PWM Output C.
May be configured for tri-state during Enhanced PWM shutdown events.
May be configured for tri-state during Enhanced PWM shutdown events.
CCP9
0
O
DIG
CCP9 Compare/PWM output; takes priority over port data.
1
I
ST
CCP9 capture input.
REFO
x
O
DIG
Reference output clock.
AD11
)
x
O
DIG
External memory interface, Address/Data Bit 11 output.
x
I
TTL
External memory interface, Data Bit 11 input.
RE4/P3B/
CCP8/AD12
CCP8/AD12
RE4
0
O
DIG
LATE<4> data output.
1
I
ST
PORTE<4> data input.
P3B
0
O
—
ECCP3 PWM Output B.
May be configured for tri-state during Enhanced PWM shutdown events.
May be configured for tri-state during Enhanced PWM shutdown events.
CCP8
0
O
DIG
CCP8 compare/PWM output; takes priority over port data.
1
I
ST
CCP8 capture input.
AD12
x
O
DIG
External memory interface, Address/Data Bit 12 output.
x
I
TTL
External memory interface, Data Bit 12 input.
RE5/P1C/
CCP7/AD13
CCP7/AD13
RE5
0
O
DIG
LATE<5> data output.
1
I
ST
PORTE<5> data input.
P1C
0
O
—
ECCP1 PWM Output C.
May be configured for tri-state during Enhanced PWM shutdown events.
May be configured for tri-state during Enhanced PWM shutdown events.
CCP7
0
O
DIG
CCP7 compare/PWM output; takes priority over port data.
1
I
ST
CCP7 capture input.
AD13
x
O
DIG
External memory interface, Address/Data Bit 13 output.
x
I
TTL
External memory interface, Data Bit 13 input.
RE6/P1B/
CCP6/AD14
CCP6/AD14
RE6
0
O
DIG
LATE<6> data output.
1
I
ST
PORTE<6> data input.
P1B
0
O
—
ECCP1 PWM Output B.
May be configured for tri-state during Enhanced PWM shutdown events.
May be configured for tri-state during Enhanced PWM shutdown events.
CCP6
0
O
DIG
CCP6 compare/PWM output; takes priority over port data.
1
I
ST
CCP9 capture input.
AD14
x
O
DIG
External memory interface, Address/Data Bit 14 output.
x
I
TTL
External memory interface, Data Bit 14 input.
TABLE 12-9:
PORTE FUNCTIONS (CONTINUED)
Pin Name
Function
TRIS
Setting
I/O
I/O
Type
Description
Legend:
O = Output, I = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Trigger Buffer Input,
x
x
= Don’t care (TRIS bit does not affect port direction or is overridden for this option).
Note
1:
Alternate assignment for ECCP2 when the CCP2MX Configuration bit is cleared and in Microcontroller mode.
2:
This feature is only available on PIC18F8XKXX devices.