Mikroelektronika MikroE Development Kits MIKROE-1209 Data Sheet
Product codes
MIKROE-1209
dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814
DS70616F-page 42
Preliminary
© 2009-2012 Microchip Technology Inc.
3.7
CPU Control Registers
REGISTER 3-1:
SR: CPU STATUS REGISTER
R/W-0
R/W-0
R/W-0
R/W-0
R/C-0
R/C-0
R -0
R/W-0
OA
(1)
OB
(1)
SA
(1,4)
SB
(1,4)
OAB
(1)
SAB
(1)
DA
(1)
DC
bit 15
bit 8
R/W-0
(2,3)
R/W-0
(2,3)
R/W-0
(2,3)
R-0
R/W-0
R/W-0
R/W-0
R/W-0
IPL<2:0>
RA
N
OV
Z
C
bit 7
bit 0
Legend:
U = Unimplemented bit, read as ‘0’
R = Readable bit
W = Writable bit
C = Clearable bit
-n = Value at POR
‘1’= Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
OA: Accumulator A Overflow Status bit
(1)
1 = Accumulator A has overflowed
0 = Accumulator A has not overflowed
0 = Accumulator A has not overflowed
bit 14
OB: Accumulator B Overflow Status bit
(1)
1 = Accumulator B has overflowed
0 = Accumulator B has not overflowed
0 = Accumulator B has not overflowed
bit 13
SA: Accumulator A Saturation ‘Sticky’ Status bit
(1,4)
1 = Accumulator A is saturated or has been saturated at some time
0 = Accumulator A is not saturated
0 = Accumulator A is not saturated
bit 12
SB: Accumulator B Saturation ‘Sticky’ Status bit
(1,4)
1 = Accumulator B is saturated or has been saturated at some time
0 = Accumulator B is not saturated
0 = Accumulator B is not saturated
bit 11
OAB: OA || OB Combined Accumulator Overflow Status bit
(1)
1 = Accumulators A or B have overflowed
0 = Neither Accumulators A or B have overflowed
0 = Neither Accumulators A or B have overflowed
bit 10
SAB: SA || SB Combined Accumulator ‘Sticky’ Status bit
(1)
1 = Accumulators A or B are saturated or have been saturated at some time
0 = Neither Accumulator A or B are saturated
0 = Neither Accumulator A or B are saturated
bit 9
DA: DO Loop Active bit
(1)
1 = DO loop in progress
0 = DO loop not in progress
0 = DO loop not in progress
bit 8
DC: MCU ALU Half Carry/Borrow bit
1 = A carry-out from the 4th low order bit (for byte-sized data) or 8th low order bit (for word-sized data)
1 = A carry-out from the 4th low order bit (for byte-sized data) or 8th low order bit (for word-sized data)
of the result occurred
0 = No carry-out from the 4th low order bit (for byte-sized data) or 8th low order bit (for word-sized
data) of the result occurred
Note 1: This bit is available on dsPIC33EPXXX(GP/MC/MU)806/810/814 devices only.
2: The IPL<2:0> bits are concatenated with the IPL<3> bit (CORCON<3>) to form the CPU Interrupt Priority
Level. The value in parentheses indicates the IPL, if IPL<3> = 1.
3: The IPL<2:0> Status bits are read only when NSTDIS = 1 (INTCON1<15>).
4: A data write to the SR register can modify the SA and SB bits by either a data write to SA and SB or by
4: A data write to the SR register can modify the SA and SB bits by either a data write to SA and SB or by
clearing the SAB bit. To avoid a possible SA or SB bit write race condition, the SA and SB bits should not
be modified using bit operations.
be modified using bit operations.