Quickcool Radio modules KEYFOB-MF1K-03ABS-BU Data Sheet

MF1S50YYX

All information provided in this document is subject to legal disclaimers.

© NXP B.V. 2011. All rights reserved.

All timing can be measured according to ISO/IEC 14443-3 frame specification as shown 
for the Frame Delay Time in 

. For more details refer to 

 and 

. 

The frame delay time from PICC to PCD must be at least 87 

μs. 

 

Remark: Due to the coding of commands, the measured timings usually excludes (a part 
of) the end of communication. This needs to be considered, when comparing the specified 
with the measured times.

The MIFARE Classic uses a 4 bit ACK / NAK as shown in 

 

last data bit transmitted by the PCD

FDT = (n* 128 + 84)/fc

256/fc

end of communication (E)

128/fc

logic ''1''

128/fc

start of

communication (S)

first modulation of the PICC

FDT = (n* 128 + 20)/fc

256/fc

end of communication (E)

T

ACK

, T

NAK

128/fc

logic ''0''

128/fc

start of

communication (S)

Ah

Acknowledge (ACK)

0h to 9h, Bh to Fh

NAK