STMicroelectronics Fully integrated stepper motor driver mounting the L6472 in a high power PowerSO package EVAL6472PD EVAL6472PD Data Sheet

20/70

DocID022729 Rev 3

At the end of power-up, the device state is the following:


Registers are set to default



Internal logic is driven by the internal oscillator and a 2 MHz clock is provided by the 
OSCOUT pin



Bridges are disabled (High Z)



UVLO bit in the STATUS register is forced low (fail condition)



FLAG output is forced low.

During power-up the device is under reset (all logic IO disabled and power bridges in high-
impedance state) until the following conditions are satisfied:


V

S

 is greater than V

SthOn



V

REG

 is greater than V

REGth

 = 2.8 V (typ.)



Internal oscillator is operative.

Any motion command causes the device to exit from High Z state (HardStop and SoftStop 
included).

Pins CS, CK, SDI, STCK, SW and STBY\RST are TTL/CMOS 3.3 V - 5 V compatible logic 
inputs.

Pin SDO is a TTL/CMOS compatible logic output. The VDD pin voltage sets the logic output 
pin voltage range; when it is connected to VREG or a 3.3 V external supply voltage, the 
output is 3.3 V compatible. When VDD is connected to a 5 V supply voltage, SDO is 5 V 
compatible. 

VDD is not internally connected to V

REG

, an external connection is always needed. 

A 10 µF capacitor should be connected to the VDD pin in order to obtain a proper operation.

Pins FLAG and BUSY\SYNC are open drain outputs.

To ensure the correct driving of the high-side integrated MOSFETs, a voltage higher than 
the motor power supply voltage needs to be applied to the Vboot pin. The high-side gate 
driver supply voltage Vboot is obtained through an oscillator and a few external components 
realizing a charge pump (see