STMicroelectronics HVLED805 Evaluation Board EVALHVLED805 EVALHVLED805 Data Sheet
Product codes
EVALHVLED805
Application information
HVLED805
22/29
Doc ID 18077 Rev 1
This offset is proportional to V
IN
and is used to compensate the current overshoot,
according to the formula:
Equation 13
Finally, the R
dmg
resistor can be calculated as follows:
Equation 14
In this case the peak drain current does not depend on input voltage anymore.
One more consideration concerns the R
dmg
value: during MOSFET’s ON-time, the current
sourced by the DMG pin, I
DMG
, is compared with an internal reference current I
DMGON
(-50
µA typical).
If I
DMG
< I
DMGON
, the brownout function is activated and the IC is shut-down.
This feature is especially important when the auxiliary winding is accidentally disconnected
and considerably increases the end-product’s safety and reliability.
and considerably increases the end-product’s safety and reliability.
5.7
Burst-mode operation at no load or very light load
When the voltage at the COMP pin falls 65 mV below a threshold fixed internally at a value,
V
V
COMPBM
, the IC is disabled with the MOSFET kept in OFF state and its consumption
reduced at a lower value to minimize Vcc capacitor discharge.
In this condition the converter operates in burst-mode (one pulse train every T
START
=500
µs), with minimum energy transfer.
As a result of the energy delivery stop, the output voltage decreases: after 500 µs the
controller switches-on the MOSFET again and the sampled voltage on the DMG pin is
compared with the internal reference. If the voltage on the EA output, as a result of the
comparison, exceeds the V
controller switches-on the MOSFET again and the sampled voltage on the DMG pin is
compared with the internal reference. If the voltage on the EA output, as a result of the
comparison, exceeds the V
COMPL
threshold, the device restarts switching, otherwise it stays
OFF for another 500 µs period.
In this way the converter will work in burst-mode with a nearly constant peak current defined
by the internal disable level. A load decrease will then cause a frequency reduction, which
can go down even to few hundred hertz, thus minimizing all frequency-related losses and
making it easier to comply with energy saving regulations. This kind of operation, shown in
the timing diagrams of
by the internal disable level. A load decrease will then cause a frequency reduction, which
can go down even to few hundred hertz, thus minimizing all frequency-related losses and
making it easier to comply with energy saving regulations. This kind of operation, shown in
the timing diagrams of
along with the others previously described, is noise-free
since the peak current is low
dmg
FF
IN
SENSE
p
d
IN
R
m
R
V
R
L
T
V
⋅
⋅
=
⋅
⋅
SENSE
d
FF
p
PRI
AUX
dmg
R
T
R
L
N
N
R
⋅
⋅
⋅
=