STMicroelectronics EVAL BOARD FOR L6563 EVL6563H-250W EVL6563H-250W Data Sheet
Product codes
EVL6563H-250W
Application information
L6563H
36/49
Doc ID 16047 Rev 3
Figure 52.
Timing diagram: normal power-up and power-down sequences
As the Vcc voltage reaches the start-up threshold (12 V typ.) the low-voltage chip starts
operating and the HV generator is cut off by the Vcc_OK signal asserted high. The device is
powered by the energy stored in the Vcc capacitor until the self-supply circuit (we assume
that it is made with an auxiliary winding in the transformer of the cascaded dc-dc converter
and a steering diode) develops a voltage high enough to sustain the operation. The residual
consumption of this circuit is just the one on the 15 M
operating and the HV generator is cut off by the Vcc_OK signal asserted high. The device is
powered by the energy stored in the Vcc capacitor until the self-supply circuit (we assume
that it is made with an auxiliary winding in the transformer of the cascaded dc-dc converter
and a steering diode) develops a voltage high enough to sustain the operation. The residual
consumption of this circuit is just the one on the 15 M
Ω resistor (10 mW at 400 Vdc),
typically 50-70 times lower, under the same conditions, as compared to a standard start-up
circuit made with external dropping resistors.
circuit made with external dropping resistors.
At converter power-down the dc-dc converter loses regulation as soon as the input voltage
is so low that either peak current or maximum duty cycle limitation is tripped. Vcc then drops
and stops IC activity as it falls below the UVLO threshold (9.5 V typ.). The Vcc_OK signal is
de-asserted as the Vcc voltage goes below a threshold VCCrestart located at about 6 V.
The HV generator can now restart. However, if Vin < VHVstart, HV_EN is de-asserted too
and the HV generator is disabled. This prevents converter's restart attempts and ensures
monotonic output voltage decay at power-down in systems where brownout protection (see
the relevant section) is not used.
is so low that either peak current or maximum duty cycle limitation is tripped. Vcc then drops
and stops IC activity as it falls below the UVLO threshold (9.5 V typ.). The Vcc_OK signal is
de-asserted as the Vcc voltage goes below a threshold VCCrestart located at about 6 V.
The HV generator can now restart. However, if Vin < VHVstart, HV_EN is de-asserted too
and the HV generator is disabled. This prevents converter's restart attempts and ensures
monotonic output voltage decay at power-down in systems where brownout protection (see
the relevant section) is not used.
If the device detects a fault due to feedback failure the pin PWM_LATCH is asserted high
(see “Feedback failure protection” section for more details) and, in order to maintain alive
this signal to be provided to the DC-DC converter, the internal VCCrestart is brought up to
over the VccOff (Turn-off threshold). As a result, shown in
(see “Feedback failure protection” section for more details) and, in order to maintain alive
this signal to be provided to the DC-DC converter, the internal VCCrestart is brought up to
over the VccOff (Turn-off threshold). As a result, shown in
, the voltage at pin Vcc,
oscillates between its turn-on and turn-off thresholds until the HV bus is recycled and drops
below the start up threshold of the HV generator.
below the start up threshold of the HV generator.
The High Voltage Start-up circuitry is capable to guarantee a safe behavior in case of short
circuit present on the dc-dc output when the Vcc of both controllers are generated by the
same auxiliary winding. The
circuit present on the dc-dc output when the Vcc of both controllers are generated by the
same auxiliary winding. The
shows how the PFC manages the Vcc cycling and
the associated power transfer. At short circuit the auxiliary circuit is no longer able to sustain
the Vcc which start dropping; reaching its VccOFF threshold the IC stops switching, reduces
the Vcc which start dropping; reaching its VccOFF threshold the IC stops switching, reduces
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