Intel 575 LF80537NF0411M User Manual
Product codes
LF80537NF0411M
R
Specification Update
33
V49.
Control Register 2 (CR2) Can be Updated during a REP MOVS/STOS Instruction
with Fast Strings Enabled
Problem:
Under limited circumstances, while executing a REP MOVS/STOS string instruction with fast strings
enabled, it is possible for the value in CR2 to be changed as a result of an interim paging event, normally
invisible to the user. Any higher priority architectural event that arrives and is handled while the interim
paging event is occurring may see the modified value of CR2.
enabled, it is possible for the value in CR2 to be changed as a result of an interim paging event, normally
invisible to the user. Any higher priority architectural event that arrives and is handled while the interim
paging event is occurring may see the modified value of CR2.
Implication: The value in CR2 is correct at the time that an architectural page fault is signaled. Intel has not observed
this erratum with any commercially available software.
Workaround: None Identified
Status:
For the steppings affected see the Summary Tables of Changes.
V50.
Writing the Local Vector Table (LVT) when an Interrupt is Pending May Cause an
Unexpected Interrupt
Unexpected Interrupt
Problem:
If a local interrupt is pending when the LVT entry is written, an interrupt may be taken on the
new interrupt vector even if the mask bit is set.
new interrupt vector even if the mask bit is set.
Implication: An interrupt may immediately be generated with the new vector when a LVT entry is written, even if the
new LVT entry has the mask bit set. If there is no Interrupt Service Routine (ISR) set up for that vector
the system will GP fault. If the ISR does not do an End of Interrupt (EOI) the bit for the vector will be
left set in the in-service register and mask all interrupts at the same or lower priority.
the system will GP fault. If the ISR does not do an End of Interrupt (EOI) the bit for the vector will be
left set in the in-service register and mask all interrupts at the same or lower priority.
Workaround: Any vector programmed into an LVT entry must have an ISR associated with it, even if that vector was
programmed as masked. This ISR routine must do an EOI to clear any unexpected interrupts that may
occur. The ISR associated with the spurious vector does not generate an EOI, therefore the spurious
vector should not be used when writing the LVT.
occur. The ISR associated with the spurious vector does not generate an EOI, therefore the spurious
vector should not be used when writing the LVT.
Status:
For the steppings affected, see the Summary Tables of Changes.
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