ADATA Extreme Edition DDR2 800G 4GB-kit AD2800G002GOU2 User Manual

Product codes
AD2800G002GOU2
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HYQVE1B16_DDR2-800G(CL=5)_2GB(128Mx8_Pb free)     Rev.0       2009/02/12             Page 2 of 7 
General Description
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The ADATA’s HYQVE1B16 is a 256Mx64 bits 2GB DDR2-800(CL5) SDRAM over clocking memory module, 
The SPD is programmed to JEDEC standard latency 800Mbps timing of 5-5-5-18 at 1.8V. The module is composed 
of sixteen 128Mx8 bits CMOS DDR2 SDRAMs in FBGA package and one 2Kbit EEPROM in 8pin TSSOP (TSOP) 
package on a 240pin glass–epoxy printed circuit board. 
The HYQVE1B16 is a Dual In-line Memory Module and intended for mounting onto 240-pins edge connector 
sockets. Synchronous design allows precise cycle control with the use of system clock. Data I/O transactions are 
possible on both edges of DQS. Range of operating frequencies, programmable latencies and burst lengths allow 
the same device to be useful for a variety of high bandwidth, high performance memory system applications.
Features
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• Power supply(Normal): VDD & VDDQ = 1.8V ± 0.1V 
• 1.8V (SSTL_18 compatible) I/O 
• Timing Reference 
      - DDR2 800 CL5-5-5-18 at 1.8V 
      - DDR2 800 CL5-5-5-12 at 2.0V 
• Burst Length: 4, 8 
• Programmable Additive Latency: 0, 1, 2, 3, 4 
• Bi-directional, differential data strobe (DQS and /DQS) 
• Differential clock input (CK, /CK) operation 
• DLL aligns DQ and DQS transition with CK transition 
• Double-data-rate architecture. 
• Auto & Self refresh 
• Average Refresh period 7.8
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• Off-Chip Driver (OCD) Impedance Adjustment 
• On Die Termination (ODT) 
• Lead-free products are RoHS compliant 
• EEPROM VDDSPD=3.3V (Typical) 
• PCB Height 30.00mm (1.181”), Double sided component 
• Clock Cycle Time (tCK):   
   - DDR2-800 tCK=2.5ns 
• Refresh to Active/Refresh Command Time (tRFC): 127.5ns
HYQVE1B16
DDR2-800G(CL5) 240-Pin O.C. U-DIMM 
2GB (256M x 64-bits)