ADATA Extreme Edition DDR2 800+ 2GB-kit AD2800E001GOU2 User Manual
Product codes
AD2800E001GOU2
ADQVD1A08_DDR2-800+(CL4)_1GB(128Mx8_Pb free) Rev.1 2008/09/17 Page 3 of 6
Pin Description
PIN
NAME
FUNCTION
CK0~CK2,
/CK0~/CK2
System Clock
Active on the positive and negative edge to sample all inputs.
CKE0
Clock Enable
Masks system clock to freeze operation from the next clock cycle. CKE should be enabled at
least on cycle prior new command. Disable input buffers for power down in standby
/S0
Chip Select
Disables or Enables device operation by masking or enabling all input except CK, CKE and
L(U)DQM
A0~A13
Address
Row / Column address are multiplexed on the same pins.
(Row Address
A0~A13 , Column Address
:A0~A9 , Auto precharge
A10/AP)
BA0~BA2
Banks Select
Selects bank to be activated during row address latch time.
Selects bank for read / write during column address latch time.
DQ0~DQ63
Data
Data and check bit inputs / outputs are multiplexed on the same pins.
DQS0~DQS7,
/DQS0~/DQS7
Data Strobe
Bi-directional Data Strobe
DM0~DM7
Data Mask
Mask input data when DM is high.
/RAS
Row Address Strobe
Latches row addresses on the positive edge of the CK with /RAS low
/CAS
Column Address Strobe Latches Column addresses on the positive edge of the CK with /CAS low
/WE
Write Enable
Enables write operation and row recharge.
VDD / VSS
Power Supply/Ground
Power and Ground for the input buffers and the core logic.
VREF
Power Supply reference Power Supply for reference
VDDSPD
SPD Power Supply
Serial EEPROM power Supply
SDA
Serial data I/O
EEPROM serial data I/O
SCL
Serial clock
EEPROM clock input
SA0~SA2
Address in EEPROM
EEPROM address input
ODT0
On Die Termination
When high, termination resistance is enabled for all DQ, /DQ and DM pins, assuming the
function is enabled in the Extended Mode Register Set.
NC
No Connection
This pin is recommended to be left No Connection on the device.