Intel Core Duo T2350 LF80539GE0362ME User Manual

Datasheet

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entry resulting in the processor either executing for a longer time at the lowest 

operating point or running idle at a high operating point. Observations and analyses 

show this behavior should not significantly impact total power savings or performance 

score while providing power benefits in most other cases.

The processor incorporates FSB low power enhancements:

• Dynamic FSB Power Down
• BPRI# control for address and control input buffers
• Dynamic Bus Parking
• Dynamic On Die Termination disabling
• Low VCCP (I/O termination voltage)

The Intel Core Duo processor and Intel Core Solo processor incorporate the DPWR# 

signal that controls the data bus input buffers on the processor. The DPWR# signal 

disables the buffers when not used and activates them only when data bus activity 

occurs, resulting in significant power savings with no performance impact. BPRI# 

control also allows the processor address and control input buffers to be turned off 

when the BPRI# signal is inactive. Dynamic Bus Parking allows a reciprocal power 

reduction in chipset address and control input buffers when the processor deasserts its 

BR0# pin. The On Die Termination on the processor FSB buffers is disabled when the 

signals are driven low, resulting in additional power savings. The low I/O termination 

voltage is on a dedicated voltage plane independent of the core voltage, enabling low 

I/O switching power at all times. 

The Intel Core Duo processor and Intel Core Solo processor incorporate the PSI# signal 

that is asserted when the processor is in a reduced power consumption state. PSI# can 

be used to improve intermediate and light load efficiency of the voltage regulator, 

resulting in platform power savings and improved battery life. The algorithm that the 

Intel Core Duo processor and Intel Core Solo processor use for determining when to 

assert PSI# is different from the algorithm used in previous Intel® Pentium® M 

processors. 

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