Kingston Technology 4GB, 1066MHz, DDR2, Non-ECC, CL7 (7-7-7-20), DIMM (Kit of 2) KHX8500AD2K2/4G Data Sheet
Product codes
KHX8500AD2K2/4G
Memory Module Specification
T
E
C
H
N
O
L
O
G
Y
Keyed
T
E
C
H
N
O
L
O
G
Y
Document No. 4805049-001.A00
09/12/08
KHX8500AD2K2/4G
4GB (2GB 256M x 64-Bit x 2 pcs.)
PC2-8500 CL7 240-Pin DIMM Kit
Page 1
T E C H N O L O G Y
DESCRIPTION:
Kingston's KHX8500AD2K2/4G is a kit of two 256M x 64-bit 2GB (2048MB) DDR2-1066 CL7
SDRAM (Synchronous DRAM) memory modules, based on sixteen 128M x 8-bit DDR2 FBGA
components per module. Total kit capacity is 4GB (4096MB). Each module pair has been tested to
run at DDR2- 1066MHz at a latency timing of 7-7-7-20 at +1.85V to +2.0V. The SPD is programmed
to JEDEC standard latency 800Mhz timing of 6-6-6-18 at +1.8V. Each 240-pin DIMM uses gold
contact fingers and requires +1.8V. The electrical and mechanical specifications are as follows:
SDRAM (Synchronous DRAM) memory modules, based on sixteen 128M x 8-bit DDR2 FBGA
components per module. Total kit capacity is 4GB (4096MB). Each module pair has been tested to
run at DDR2- 1066MHz at a latency timing of 7-7-7-20 at +1.85V to +2.0V. The SPD is programmed
to JEDEC standard latency 800Mhz timing of 6-6-6-18 at +1.8V. Each 240-pin DIMM uses gold
contact fingers and requires +1.8V. The electrical and mechanical specifications are as follows:
FEATURES:
Power supply : Vdd: 1.8V ± 0.1V, Vddq: 1.8V ± 0.1V
Double-data-rate architecture; two data transfers per clock cycle
Bidirectional data strobe(DQS)
Differential clock inputs(CK and CK)
DLL aligns DQ and DQS transition with CK transition
Programmable Read latency 6, 5, 4 (clock)
Burst Length: 4, 8 (Interleave/nibble sequential)
Programmable Burst type (sequential & interleave)
Timing Reference: 6-6-6-18 at +1.8V / 7-7-7-20 at +1.85 to +2.0V
Edge aligned data output, center aligned data input
Auto & Self refresh, 7.8us refresh interval (8K/64ms refresh)
Serial presence detect with EEPROM
High Performance Heat Spreader
Double-data-rate architecture; two data transfers per clock cycle
Bidirectional data strobe(DQS)
Differential clock inputs(CK and CK)
DLL aligns DQ and DQS transition with CK transition
Programmable Read latency 6, 5, 4 (clock)
Burst Length: 4, 8 (Interleave/nibble sequential)
Programmable Burst type (sequential & interleave)
Timing Reference: 6-6-6-18 at +1.8V / 7-7-7-20 at +1.85 to +2.0V
Edge aligned data output, center aligned data input
Auto & Self refresh, 7.8us refresh interval (8K/64ms refresh)
Serial presence detect with EEPROM
High Performance Heat Spreader
PCB : Height 1.180” (30.00mm), double sided component
PERFORMANCE:
Clock Cycle Time (tCK) CL=5
2.5ns (min.) / 8ns (max.)
Row Cycle Time (tRC)
60ns (min.)
Refresh to Active/Refresh Command Time (tRFC)
127.5ns
Row Active Time (tRAS)
45ns (min.) / 70,000ns (max.)
Single Power Supply of
+1.8V (+/- .1V)
Power
1.584 W (operating per module)
UL Rating
94 V - 0
Operating Temperature
0
o
C to 55
o
C
Storage Temperature
-55
o
C to +125
o
C