IBM Intel Xeon E7430 44E4470 Data Sheet
Product codes
44E4470
Intel® Xeon® Processor 7400 Series Datasheet
133
Debug Tools Specifications
8
Debug Tools Specifications
Please refer to the appropriate platform design guidelines for information regarding
debug tool specifications.
debug tool specifications.
provides collateral details.
8.1
Debug Port System Requirements
The Intel® Xeon® Processor 7400 Series debug port is the command and control
interface for the In-Target Probe (ITP) debugger. The ITP enables run-time control of
the processors for system debug. The debug port, which is connected to the FSB, is a
combination of the system JTAG and execution signals. There are several mechanical,
electrical and functional constraints on the debug port that must be followed. The
mechanical constraint requires the debug port connector to be installed in the system
with adequate physical clearance. Electrical constraints exist due to the mixed high and
low speed signals of the debug port for the processor. While the JTAG signals operate at
a maximum of 75 MHz, the execution signals operate at the common clock FSB
frequency. The functional constraint requires the debug port to use the JTAG system via
a handshake and multiplexing scheme.
interface for the In-Target Probe (ITP) debugger. The ITP enables run-time control of
the processors for system debug. The debug port, which is connected to the FSB, is a
combination of the system JTAG and execution signals. There are several mechanical,
electrical and functional constraints on the debug port that must be followed. The
mechanical constraint requires the debug port connector to be installed in the system
with adequate physical clearance. Electrical constraints exist due to the mixed high and
low speed signals of the debug port for the processor. While the JTAG signals operate at
a maximum of 75 MHz, the execution signals operate at the common clock FSB
frequency. The functional constraint requires the debug port to use the JTAG system via
a handshake and multiplexing scheme.
In general, the information in this chapter may be used as a basis for including all run-
control tools in Intel® Xeon® Processor 7400 Series-based systems designs including
tools from vendors other than Intel.
control tools in Intel® Xeon® Processor 7400 Series-based systems designs including
tools from vendors other than Intel.
Note:
The debug port and JTAG signal chain must be designed into the processor board to
utilize the XDP for debug purposes except for interposer solutions.
8.2
Logic Analyzer Interface (LAI)
Intel is working with two logic analyzer vendors to provide logic analyzer interfaces
(LAIs) for use in debugging Intel® Xeon® Processor 7400 Series systems. Tektronix
and Agilent should be contacted to obtain specific information about their logic analyzer
interfaces. The following information is general in nature. Specific information must be
obtained from the logic analyzer vendor.
(LAIs) for use in debugging Intel® Xeon® Processor 7400 Series systems. Tektronix
and Agilent should be contacted to obtain specific information about their logic analyzer
interfaces. The following information is general in nature. Specific information must be
obtained from the logic analyzer vendor.
Due to the complexity of Intel® Xeon® Processor 7400 Series-based multiprocessor
systems, the LAI is critical in providing the ability to probe and capture FSB signals.
There are two sets of considerations to keep in mind when designing a Intel® Xeon®
Processor 7400 Series-based system that can make use of an LAI: mechanical and
electrical.
systems, the LAI is critical in providing the ability to probe and capture FSB signals.
There are two sets of considerations to keep in mind when designing a Intel® Xeon®
Processor 7400 Series-based system that can make use of an LAI: mechanical and
electrical.
8.2.1
Mechanical Considerations
The LAI is installed between the processor socket and the processor. The LAI plugs into
the socket, while the processor plugs into a socket on the LAI. Cabling that is part of
the LAI egresses the system to allow an electrical connection between the processor
and a logic analyzer. The maximum volume occupied by the LAI, known as the keepout
volume, as well as the cable egress restrictions, should be obtained from the logic
analyzer vendor. System designers must make sure that the keepout volume remains
unobstructed inside the system. In some cases, it is known that some of the electrolytic
capacitors fall inside of the keepout volume for the LAI. In this case, it is necessary to
move these capacitors to the backside of the board before using the LAI. Additionally,
note that it is possible that the keepout volume reserved for the LAI may include
the socket, while the processor plugs into a socket on the LAI. Cabling that is part of
the LAI egresses the system to allow an electrical connection between the processor
and a logic analyzer. The maximum volume occupied by the LAI, known as the keepout
volume, as well as the cable egress restrictions, should be obtained from the logic
analyzer vendor. System designers must make sure that the keepout volume remains
unobstructed inside the system. In some cases, it is known that some of the electrolytic
capacitors fall inside of the keepout volume for the LAI. In this case, it is necessary to
move these capacitors to the backside of the board before using the LAI. Additionally,
note that it is possible that the keepout volume reserved for the LAI may include