IBM Intel Xeon E7430 44E4470 Data Sheet
Product codes
44E4470
Electrical Specifications
20
Intel® Xeon® Processor 7400 Series Datasheet
2.5
Reserved, Unused, or Test Signals
All Reserved signals must remain unconnected. Connection of these signals to V
CC
, V
TT
,
V
SS
, or to any other signal (including each other) can result in component malfunction
for a pin listing of the processor
and the location of all Reserved signals.
For reliable operation, always connect unused inputs or bidirectional signals to an
appropriate signal level. Unused active high inputs, should be connected through a
resistor to ground (V
appropriate signal level. Unused active high inputs, should be connected through a
resistor to ground (V
SS
). Unused outputs can be left unconnected; however, this may
interfere with some TAP functions, complicate debug probing, and prevent boundary
scan testing. A resistor must be used when tying bidirectional signals to power or
ground. When tying any signal to power or ground, a resistor will also allow for system
testability. Resistor values should be within ± 20% of the impedance of the baseboard
trace for FSB signals, unless otherwise noticed in the appropriate platform design
guidelines. For unused AGTL+ input or I/O signals, use pull-up resistors of the same
value as the on-die termination resistors (R
scan testing. A resistor must be used when tying bidirectional signals to power or
ground. When tying any signal to power or ground, a resistor will also allow for system
testability. Resistor values should be within ± 20% of the impedance of the baseboard
trace for FSB signals, unless otherwise noticed in the appropriate platform design
guidelines. For unused AGTL+ input or I/O signals, use pull-up resistors of the same
value as the on-die termination resistors (R
TT
TAP, Asynchronous GTL+ inputs, and Asynchronous GTL+ outputs do not include on-die
termination. Inputs and utilized outputs must be terminated on the baseboard. Unused
outputs may be terminated on the baseboard or left unconnected. Note that leaving
unused outputs unterminated may interfere with some TAP functions, complicate debug
probing, and prevent boundary scan testing. Signal termination for these signal types
is discussed in the appropriate platform design guidelines.
termination. Inputs and utilized outputs must be terminated on the baseboard. Unused
outputs may be terminated on the baseboard or left unconnected. Note that leaving
unused outputs unterminated may interfere with some TAP functions, complicate debug
probing, and prevent boundary scan testing. Signal termination for these signal types
is discussed in the appropriate platform design guidelines.
For each processor socket, connect the TESTIN1 and TESTIN2 signals together, then
terminate the net with a 51 Ω resistor to V
terminate the net with a 51 Ω resistor to V
TT
.
The TESTHI signals may use individual pull-up resistors or be grouped together as
detailed below.
detailed below.
• TESTHI[1:0] - can be grouped together with a single pull-up to V
TT
2.6
Front Side Bus Signal Groups
The FSB signals have been combined into groups by buffer type. AGTL+ input signals
have differential input buffers, which use GTLREF_DATA_MID, GTLREF_DATA_END,
GTLREF_ADD_MID, and GTLREF_ADD_END as reference levels. In this document, the
term “AGTL+ Input” refers to the AGTL+ input group as well as the AGTL+ I/O group
when receiving. Similarly, “AGTL+ Output” refers to the AGTL+ output group as well as
the AGTL+ I/O group when driving. AGTL+ asynchronous outputs can become active
anytime and include an active PMOS pull-up transistor to assist during the first clock of
a low-to-high voltage transition.
have differential input buffers, which use GTLREF_DATA_MID, GTLREF_DATA_END,
GTLREF_ADD_MID, and GTLREF_ADD_END as reference levels. In this document, the
term “AGTL+ Input” refers to the AGTL+ input group as well as the AGTL+ I/O group
when receiving. Similarly, “AGTL+ Output” refers to the AGTL+ output group as well as
the AGTL+ I/O group when driving. AGTL+ asynchronous outputs can become active
anytime and include an active PMOS pull-up transistor to assist during the first clock of
a low-to-high voltage transition.
With the implementation of a source synchronous data bus comes the need to specify
two sets of timing parameters. One set is for common clock signals whose timings are
specified with respect to rising edge of BCLK0 (ADS#, HIT#, HITM#, etc.) and the
second set is for the source synchronous signals which are relative to their respective
strobe lines (data and address) as well as rising edge of BCLK0. Asynchronous signals
are still present (A20M#, IGNNE#, etc.) and can become active at any time during the
clock cycle.
two sets of timing parameters. One set is for common clock signals whose timings are
specified with respect to rising edge of BCLK0 (ADS#, HIT#, HITM#, etc.) and the
second set is for the source synchronous signals which are relative to their respective
strobe lines (data and address) as well as rising edge of BCLK0. Asynchronous signals
are still present (A20M#, IGNNE#, etc.) and can become active at any time during the
clock cycle.
and asynchronous.