Intel 1.00 GHz BX80530F1000256 Data Sheet

17

The Stop-Grant state on the processor is entered when the STPCLK# signal is asserted.

Since the AGTL+ signal pins receive power from the system bus, these pins should not be driven 
(allowing the level to return to V

TT

) for minimum power drawn by the termination resistors in this 

state. In addition, all other input pins on the system bus should be driven to the inactive state.

BINIT# will not be serviced while the processor is in Stop-Grant state. The event will be latched 
and can be serviced by software upon exit from Stop-Grant state.

FLUSH# will not be serviced during Stop-Grant state.

RESET# will cause the processor to immediately initialize itself, but the processor will stay in 
Stop-Grant state. A transition back to the Normal state will occur with the deassertion of the 
STPCLK# signal.

A transition to the HALT/Grant Snoop state will occur when the processor detects a snoop on the 
system bus (see 

). A transition to the Sleep state (see 

) will occur with the 

assertion of the SLP# signal.

While in the Stop-Grant State, SMI#, INIT#, and LINT[1:0] will be latched by the processor, and 
only serviced when the processor returns to the Normal State. Only one occurrence of each event 
will be recognized upon return to the Normal state.

The processor will respond to snoop transactions on the Celeron processor system bus while in 
Stop-Grant state or in AutoHALT Power Down state. During a snoop transaction, the processor 
enters the HALT/Grant Snoop state. The processor will stay in this state until the snoop on the Intel 
Celeron processor system bus has been serviced (whether by the processor or another agent on the 
Intel Celeron processor system bus). After the snoop is serviced, the processor will return to the 
Stop-Grant state or AutoHALT Power Down state, as appropriate.

The Sleep state is a very low power state in which the processor maintains its context, maintains 
the phase-locked loop (PLL), and has stopped all internal clocks. The Sleep state can only be 
entered from Stop-Grant state. Once in the Stop-Grant state, the SLP# pin can be asserted, causing 
the processor to enter the Sleep state. The SLP# pin is not recognized in the Normal or AutoHALT 
states.

Snoop events that occur while in Sleep State or during a transition into or out of Sleep state will 
cause unpredictable behavior.

In the Sleep state, the processor is incapable of responding to snoop transactions or latching 
interrupt signals. No transitions or assertions of signals (with the exception of SLP# or RESET#) 
are allowed on the system bus while the processor is in Sleep state. Any transition on an input 
signal before the processor has returned to Stop-Grant state will result in unpredictable behavior.

If RESET# is driven active while the processor is in the Sleep state, and held active as specified in 
the RESET# pin specification, then the processor will reset itself, ignoring the transition through 
Stop-Grant State. If RESET# is driven active while the processor is in the Sleep State, the SLP# 
and STPCLK# signals should be deasserted immediately after RESET# is asserted to ensure the 
processor correctly executes the Reset sequence.