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Intel III Xeon 667 MHz 80526KZ667256 Data Sheet

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80526KZ667256
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PENTIUM® III XEON™ PROCESSOR AT 600 MHz to 1  GHz with 256KB L2 Cache
APPENDIX
101
pins. The power supply must supply the voltage that is requested by these pins, or disable itself. See section 3.9 for the
maximum rating for these signals.
10.1.63 VIN_SENSE
VIN_SENSE (formerly called CPU_SENSE) is routed from edge-connector pin A56 to the VCC_CORE power plane.
VIN_SENSE provides remote sensing capabilities for the voltage seen at the input of the OCVR.
NOTE:  Pentium III Xeon processors at  600 MHz+ support either +2.8V, +5V or +12V VCC_CORE voltages
depending on the version of OCVR. Therefore, any sensing logic must be capable of tolerating the selected
VCC_CORE voltage (+2.8/+5V/+12V).
10.1.64 WP (I)
WP (Write Protect) can be used to write protect the scratch EEPROM. A high level write-protects the scratch EEPROM.
10.2 Signal Summaries
The following tables list attributes of the Pentium III Xeon processor at 600 MHz+ output, input, and I/O signals.
Table  53.  Output Signals
Name
Active Level
Clock
Signal Group
FERR#
Low
Asynch
CMOS Output
IERR#
Low
Asynch
CMOS Output
PRDY#
Low
BCLK
AGTL+ Output
SMBALERT#
Low
Asynch
SMBus Output
TDO
High
TCK
TAP Output
THERMTRIP#
Low
Asynch
CMOS Output
VID_CORE[4:0]
High
Asynch
Power/Other
VID_L2[4:0]
High
Asynch
Power/Other
CPU_SENSE
high
Asynch
Power/Other
L2_SENSE
high
Asynch
Power/Other
OCVR_OK
high
Asynch
Power/Other
Table  54.  Input Signals
Name
Active Level
Clock
Signal Group
Qualified
A20M#
Low
Asynch
CMOS Input
Always
BPRI#
Low
BCLK
AGTL+ Input
Always
BR[3:1]#
Low
BCLK
AGTL+ Input
Always
BCLK
High
—
System Bus Clock
Always
DEFER#
Low
BCLK
AGTL+ Input
Always
FLUSH#
Low
Asynch
CMOS Input
Always 
2
IGNNE#
Low
Asynch
CMOS Input
Always 
2
INIT#
Low
Asynch
CMOS Input
Always 
2
INTR
High
Asynch
CMOS Input
APIC disabled mode