Intel III Xeon 667 MHz 80526KZ667256 Data Sheet

Product codes
80526KZ667256
Page of 103
PENTIUM® III XEON™ PROCESSOR AT 600 MHz to 1  GHz with 256KB L2 Cache
PROCESSOR FEATURES
48
uniquely determined for each unit. The procedure causes each unit to dissipate its maximum power (which
can vary from unit to unit) while at the same time maintaining the thermal plate at its maximum specified
operating temperature. Correctly used, this feature permits an efficient thermal solution while preserving data
integrity.
The thermal byte reading can be used in conjunction with the Thermal Reference Byte in the processor
Information ROM. Byte 9 of the processor Information ROM contains the address in the ROM of this byte,
described in more detail in Section 5.2.5. The thermal byte reading from the thermal sensor can be compared
to this Thermal Reference Byte to provide an indication of the difference between the temperature of the
processor core at the instant of the thermal byte reading and the temperature of the processor core under the
steady state conditions of high power and maximum TPLATE specifications. The nominal precision of the
least significant bit of a thermal byte is 1°C.
Reading the thermal sensor is explained in Section 5.2.6. See the  Pentium® III Xeon™ processor SMBus
Thermal Reference Guidelines
 for more details and further recommendations on the use of this feature in
Pentium III Xeon processor at 600 MHz+ based systems.
The thermal sensor feature in the processor cannot be used to measure TPLATE. The TPLATE specification
in Chapter 6 must be met regardless of the reading of the processor's thermal sensor in order to ensure
adequate cooling for the entire Pentium III Xeon processor at 600 MHz+. The thermal sensor feature is only
available while VCC_ CORE and VCC_SMB are at valid levels and the processor is not in a low-power state.
5.2.5   
THERMAL SENSOR SUPPORTED SMBUS TRANSACTIONS
The thermal sensor responds to five of the SMBus packet types: write byte, read byte, send byte, receive
byte, and ARA (Alert Response Address). The send byte packet is used for sending one-shot commands only.
The receive byte packet accesses the register commanded by the last read byte packet. If a receive byte
packet was preceded by a write byte or send byte packet more recently than a read byte packet, then the
behavior is undefined. Tables 31 through 35 diagram the five packet types. In these figures, ‘S’ represents the
SMBus start bit, ‘P’ represents a stop bit, ‘Ack’ represents an acknowledge, and ‘///’ represents a negative
acknowledge. The  thermal sensor  transmits those  bits that are shaded,  and the  SMBus host controller
transmits those bits that are non-shaded. Table 36 shows the encoding of the command byte.
Table 31.  Write Byte SMBus Packet
S
Address
Write
Ack
Command
Ack
Data
Ack
P
1
7 bits
1
1
8 bits
1
8 bits
1
1
Table 32.  Read Byte SMBus Packet
S
Address
Write
Ack
Command
Ack
S
Address
Read
Ack
Data
///
P
1
7 bits
1
1
8 bits
1
1
7 bits
1
1
8 bits
1
1
Table 33.  Send Byte SMBus Packet
S
Address
Write
Ack
Command
Ack
P
1
7 bits
1
1
8 bits
1
1
Table 34.  Receive Byte SMBus Packet
S
Address
Read
Ack
Data
///
P
1
7 bits
1
1
8 bits
1
1
Table 35.  ARA SMBus Packet
S
ARA
Read
Ack
Address
///
P
1
0001 100
1
1
Device Address
1
1
1
NOTE: