Intel III Xeon 667 MHz 80526KZ667256 Data Sheet

78

Pentium® III Xeon™ processor

at 600 MHz+ .

GND

2, 4, 6,
13, 15,
17, 19,
21, 23,

25, 27

Signal ground.

Connect all pins to signal

ground.

1. 

Resistor values with “~” preceding them can vary from the specified value; use resistor as close as possible to the value
specified.

2. 

Termination should include series (~240  ohm ) and AGTL+ termination (connected to 1.5V) resistors. Figure  30A.

3. 

Signal should be at end of daisy chain and the boundary scan chain should be partitioned into two distinct sections to
assist in debugging the system: one partition with only the processor(s) for system debug (i.e., used with the ITP) and
another with all other components for manufacturing or system test.

In general, all open drain AGTL+ outputs from the system must be retained at a proper logic level, whether or
not the debug port is installed. RESET# from the processor system should be terminated at the debug port, as
shown Figure 30. Rt should be a 150

Ω

 on RESET#.

PRDYn# should have a similar layout, however Rt should be 50

Ω

 to match board impedance rather than the

normal 150

Ω

 since there are only 2 loads on this signal.

Signals from the debug port are fed to the system from the ITP via a buffer board and a cable. If system
signals routed to the debug port (i.e. TDO, PRDYn# and RESET#) are used elsewhere in the system, then
dedicated drivers should be used to isolate the signals from reflections coming from the end of this cable. If
the Pentium® III Xeon™ processor at 600 MHz+ boundary scan signals are used elsewhere in the system,
then the TDI, TMS, TCK, and TRST# signals from the debug port should be isolated from the system signals.

In general, no signals should be left floating. Thus, signals going from the debug port to the processor system
should not be left floating. If they are left floating, there may be problems when the ITP is not plugged into the
connector.