Intel III Xeon 667 MHz 80526KZ667256 Data Sheet
Product codes
80526KZ667256
PENTIUM® III XEON™ PROCESSOR AT 600 MHz to 1 GHz with 256KB L2 Cache
APPENDIX
92
Table 51. BR[3] and BR[1:0]# Signals Rotating Interconnect,
2-Way System
Bus Signal
Agent 0 Pins
Agent 1 Pins
BREQ0#
BR0#
BR3#
BREQ1#
BR1#
BR0#
BREQ2#
N/C
N/C
BREQ3#
N/C
N/C
During power-up configuration, the central agent must assert its BR0# signal. All symmetric agents sample their BR[3:0]#
pins on active-to-inactive transition of RESET#. The pin on which the agent samples an active level determines its agent
ID. All agents then configure their BREQ[3:0]# signals to match the appropriate bus signal protocol.
pins on active-to-inactive transition of RESET#. The pin on which the agent samples an active level determines its agent
ID. All agents then configure their BREQ[3:0]# signals to match the appropriate bus signal protocol.
BR0#
BR1#
BR3#
Agent ID
L
H
H
0
H
H
L
1
10.1.15 CORE_AN_SENSE (O)
This signal is tied to the VCC seen at the processor core and represents the output of the OCVR. This signal provides the
ability to monitor the stability of the OCVR in high reliability applications. The voltage seen at this pin is the actual
operating voltage of the core with integrated L2 Cache minus IR drops due to trace routing in the Cartridge.
ability to monitor the stability of the OCVR in high reliability applications. The voltage seen at this pin is the actual
operating voltage of the core with integrated L2 Cache minus IR drops due to trace routing in the Cartridge.
10.1.16 D[63:00]# (I/O)
The D[63:00]# (Data) signals are the data signals. These signals provide a 64-bit data path between the Pentium® III
Xeon™ processor at 600 MHz+ system bus agents, and must connect the appropriate pins on all such agents. The data
driver asserts DRDY# to indicate a valid data transfer.
Xeon™ processor at 600 MHz+ system bus agents, and must connect the appropriate pins on all such agents. The data
driver asserts DRDY# to indicate a valid data transfer.
10.1.17 DBSY# (I/O)
The DBSY# (Data Bus Busy) signal is asserted by the agent responsible for driving data on the Pentium III Xeon
processor at 600 MHz+ system bus to indicate that the data bus is in use. The data bus is released after DBSY# is
deasserted. This signal must connect the appropriate pins on all Pentium III Xeon processor at 600 MHz+ system bus
agents.
processor at 600 MHz+ system bus to indicate that the data bus is in use. The data bus is released after DBSY# is
deasserted. This signal must connect the appropriate pins on all Pentium III Xeon processor at 600 MHz+ system bus
agents.
10.1.18 DEFER# (I)
The DEFER# signal is asserted by an agent to indicate that a transaction cannot be guaranteed in-order completion.
Assertion of DEFER# is normally the responsibility of all Pentium III Xeon processor at 600 MHz+ system bus agents.
Assertion of DEFER# is normally the responsibility of all Pentium III Xeon processor at 600 MHz+ system bus agents.
10.1.19 DEP[7:0]# (I/O)
The DEP[7:0]# (Data Bus ECC Protection) signals provide optional ECC protection for the data bus. They are driven by
the agent responsible for driving D[63:00]#, and must connect the appropriate pins of all Pentium III Xeon processor at
600 MHz+ system bus agents which use them. The DEP[7:0]# signals are enabled or disabled for ECC protection during
power on configuration.
the agent responsible for driving D[63:00]#, and must connect the appropriate pins of all Pentium III Xeon processor at
600 MHz+ system bus agents which use them. The DEP[7:0]# signals are enabled or disabled for ECC protection during
power on configuration.
10.1.20 DRDY# (I/O)
The DRDY# (Data Ready) signal is asserted by the data driver on each data transfer, indicating valid data on the data
bus. In a multi-cycle data transfer, DRDY# may be deasserted to insert idle clocks. This signal must connect the
appropriate pins of all Pentium III Xeon processor at 600 MHz+ system bus agents.
bus. In a multi-cycle data transfer, DRDY# may be deasserted to insert idle clocks. This signal must connect the
appropriate pins of all Pentium III Xeon processor at 600 MHz+ system bus agents.