Intel III Xeon 667 MHz 80526KZ667256 Data Sheet
Product codes
80526KZ667256
PENTIUM® III XEON™ PROCESSOR AT 600 MHz to 1 GHz with 256KB L2 Cache
APPENDIX
95
10.1.36 PICD[1:0] (I/O)
The PICD[1:0] (APIC Data) signals are used for bi-directional serial message passing on the APIC bus, and must connect
the appropriate pins of all processors and core logic or I/O APIC components on the APIC bus.
the appropriate pins of all processors and core logic or I/O APIC components on the APIC bus.
10.1.37 PRDY# (O)
The PRDY (Probe Ready) signal is a processor output used by debug tools to determine processor debug readiness.
10.1.38 PREQ# (I)
The PREQ# (Probe Request) signal is used by debug tools to request debug operation of the processors.
10.1.39 PWREN[1:0] (I)
These 2 pins are tied directly together on the processor. They can be used to detect processor presence by applying a
voltage to one pin and observing it at the other. See 3.9 for the maximum rating for this signal.
voltage to one pin and observing it at the other. See 3.9 for the maximum rating for this signal.
10.1.40 PWRGOOD (I)
The (Power Good) signal is a 2.5V tolerant processor input. The processor requires this signal to be a clean indication
that the clocks and power supplies (VCC_CORE, VCC_L2, VCC_TAP, VCC_SMB, VCC2.5) are stable and within their
that the clocks and power supplies (VCC_CORE, VCC_L2, VCC_TAP, VCC_SMB, VCC2.5) are stable and within their
specifications. Clean implies that the signal will remain low (capable of sinking leakage current), without glitches, from the
time that the power supplies are turned on, until they come within specification. The signal must then transition
monotonically to a high (2.5V) state. Figure 41 illustrates the relationship of PWRGD to other system signals. PWRGD
can be driven inactive at any time, but clocks and power must again be stable before a subsequent rising edge of
PWRGD. It must also meet the minimum pulse width specification in Table 13 and be followed by an 8 mS RESET#
pulse.
time that the power supplies are turned on, until they come within specification. The signal must then transition
monotonically to a high (2.5V) state. Figure 41 illustrates the relationship of PWRGD to other system signals. PWRGD
can be driven inactive at any time, but clocks and power must again be stable before a subsequent rising edge of
PWRGD. It must also meet the minimum pulse width specification in Table 13 and be followed by an 8 mS RESET#
pulse.
The PWRGD signal must be supplied to the processor; it is used to protect internal circuits against voltage sequencing
issues. It should be driven high throughout boundary scan operation.
issues. It should be driven high throughout boundary scan operation.
Current VRM 8.3 (on baseboard) specification requires VRM_PWRGD to be asserted when its output is within 12% of
nominal value. In the Pentium III Xeon processor at 600 MHz+, PWRGD is logically ANDed with OCVR_OK before being
applied to the core (PWRGD_CORE). According to legacy EMTS documents, RESET# negation is expected 1 mS after
seeing PWRGD_CORE becoming valid by the processor core. The OCVR is not expected to provide a valid OCVR_OK
signal assertion within 13 mS of seeing 90% of its input voltage. The delay before the assertion of OCVR_OK may cause
a race condition between RESET# and the valid PWRGD_CORE that is seen at the core. It is recommended to relax the
deassertion of RESET# to meet this critical constrain. Careful analysis needs to be done in existing platforms. Refer to
Figure 41 and Figure 42 below for new timing relationship requirements.
nominal value. In the Pentium III Xeon processor at 600 MHz+, PWRGD is logically ANDed with OCVR_OK before being
applied to the core (PWRGD_CORE). According to legacy EMTS documents, RESET# negation is expected 1 mS after
seeing PWRGD_CORE becoming valid by the processor core. The OCVR is not expected to provide a valid OCVR_OK
signal assertion within 13 mS of seeing 90% of its input voltage. The delay before the assertion of OCVR_OK may cause
a race condition between RESET# and the valid PWRGD_CORE that is seen at the core. It is recommended to relax the
deassertion of RESET# to meet this critical constrain. Careful analysis needs to be done in existing platforms. Refer to
Figure 41 and Figure 42 below for new timing relationship requirements.