Intel III Xeon 667 MHz 80526KZ667256 Data Sheet
Product codes
80526KZ667256
PENTIUM® III XEON™ PROCESSOR AT 600 MHz to 1 GHz with 256KB L2 Cache
APPENDIX
98
The RS[2:0]# (Response Status) signals are driven by the response agent (the agent responsible for completion of the
current transaction), and must connect the appropriate pins of all Pentium® III Xeon™ processor at 600 MHz+ system
bus agents.
current transaction), and must connect the appropriate pins of all Pentium® III Xeon™ processor at 600 MHz+ system
bus agents.
10.1.45 RSP# (I)
The RSP# (Response Parity) signal is driven by the response agent (the agent responsible for completion of the current
transaction) during assertion of RS[2:0]#, the signals for which RSP# provides parity protection. It must connect the
appropriate pins of all Pentium III Xeon processor at 600 MHz+ system bus agents. A correct parity signal is high if an
even number of covered signals is low and low if an odd number of covered signals are low. While RS[2:0]# = 000, RSP#
is also high, since this indicates it is not being driven by any agent guaranteeing correct parity
transaction) during assertion of RS[2:0]#, the signals for which RSP# provides parity protection. It must connect the
appropriate pins of all Pentium III Xeon processor at 600 MHz+ system bus agents. A correct parity signal is high if an
even number of covered signals is low and low if an odd number of covered signals are low. While RS[2:0]# = 000, RSP#
is also high, since this indicates it is not being driven by any agent guaranteeing correct parity
.
10.1.46 SA[2:0] (I)
The SA (Select Address) pins are decoded on the SMBus in conjunction with the upper address bits in order to maintain
unique addresses on the SMBus in a system with multiple Pentium III Xeon processors at 600 MHz+. To set an SA line
high, a pull-up resistor should be used that is no larger than 1K
unique addresses on the SMBus in a system with multiple Pentium III Xeon processors at 600 MHz+. To set an SA line
high, a pull-up resistor should be used that is no larger than 1K
Ω
. To set an SA line as low, the pin can be left
unconnected. SA2 can also be tri-stated to define additional addresses for the thermal sensor. A tri-state or “Z” state on
this pin is achieved by leaving this pin unconnected.
this pin is achieved by leaving this pin unconnected.
Of the addresses broadcast across the SMBus, the memory components claim those of the form “1010XXYZb”. The “XX”
and “Y” bits are used to enable the devices on the cartridge at adjacent addresses. The Y bit is hard-wired on the
and “Y” bits are used to enable the devices on the cartridge at adjacent addresses. The Y bit is hard-wired on the
cartridge to V SS (‘0’) for the Scratch EEPROM and pulled to VCCSMB (‘1’) for the processor Information ROM. The “XX”
bits are defined by the processor slot via the SA0 and SA1 pins on the SC330 connector. These address pins are pulled
down weakly (10 k ) on the cartridge to ensure that the memory components are in a known state in systems that do not
support the SMBus, or only support a partial implementation. The “Z” bit is the read/write bit for the serial bus transaction.
bits are defined by the processor slot via the SA0 and SA1 pins on the SC330 connector. These address pins are pulled
down weakly (10 k ) on the cartridge to ensure that the memory components are in a known state in systems that do not
support the SMBus, or only support a partial implementation. The “Z” bit is the read/write bit for the serial bus transaction.
The thermal sensor internally decodes 1 of 3 upper address patterns from the bus of the form “0011XXXZb”,
“1001XXXZb” or “0101XXXZb”. The device’s addressing, as implemented, includes a Hi-Z state for one address pin
(SA2), and therefore supports 6 unique resulting addresses. The ability of the system to drive this pin to a Hi-Z state is
dependent on the baseboard implementation (The pin must be left floating). The system should drive SA1 and SA0, and
will be pulled low (if not driven) by the 10 K-ohm pull-down resistor on the processor substrate. Driving these signals to a
Hi-Z state would cause ambiguity in the memory device address decode, possibly resulting in the devices not responding,
thus timing out or hanging the SMBus. As before, the “Z” bit is the read/write bit for the serial bus transaction. For more
information on the usage of these pins, see section 5.2.7.
“1001XXXZb” or “0101XXXZb”. The device’s addressing, as implemented, includes a Hi-Z state for one address pin
(SA2), and therefore supports 6 unique resulting addresses. The ability of the system to drive this pin to a Hi-Z state is
dependent on the baseboard implementation (The pin must be left floating). The system should drive SA1 and SA0, and
will be pulled low (if not driven) by the 10 K-ohm pull-down resistor on the processor substrate. Driving these signals to a
Hi-Z state would cause ambiguity in the memory device address decode, possibly resulting in the devices not responding,
thus timing out or hanging the SMBus. As before, the “Z” bit is the read/write bit for the serial bus transaction. For more
information on the usage of these pins, see section 5.2.7.
10.1.47 SELFSB0 (I) SELFSB1 (O)
The Pentium III Xeon processor at 600 MHz+ adds a new definition to the SELFSB [1:0] pins that is shown below .