Intel 4 1.50 GHz 80528PC021G0K User Manual
Product codes
80528PC021G0K
Intel
®
Pentium
®
4 Processor in the 423-pin Package
65
D[63:0]#
Input/
Output
D[63:0]# (Data) are the data signals. These signals provide a 64-bit data path
between the processor system bus agents, and must connect the appropriate pins
on all such agents. The data driver asserts DRDY# to indicate a valid data transfer.
between the processor system bus agents, and must connect the appropriate pins
on all such agents. The data driver asserts DRDY# to indicate a valid data transfer.
D[63:0]# are quad-pumped signals and will thus be driven four times in a common
clock period. D[63:0]# are latched off the falling edge of both DSTBP[3:0]# and
DSTBN[3:0]#. Each group of 16 data signals correspond to a pair of one DSTBP#
and one DSTBN#. The following table shows the grouping of data signals to data
strobes and DBI#.
clock period. D[63:0]# are latched off the falling edge of both DSTBP[3:0]# and
DSTBN[3:0]#. Each group of 16 data signals correspond to a pair of one DSTBP#
and one DSTBN#. The following table shows the grouping of data signals to data
strobes and DBI#.
Furthermore, the DBI# pins determine the polarity of the data signals. Each group
of 16 data signals corresponds to one DBI# signal. When the DBI# signal is active,
the corresponding data group is inverted and therefore sampled active high.
of 16 data signals corresponds to one DBI# signal. When the DBI# signal is active,
the corresponding data group is inverted and therefore sampled active high.
DBI[3:0]#
Input/
Output
DBI[3:0]# are source synchronous and indicate the polarity of the D[63:0]# signals.
The DBI[3:0]# signals are activated when the data on the data bus is inverted. The
bus agent will invert the data bus signals if more than half the bits, within the
covered group, would change level in the next cycle.
The DBI[3:0]# signals are activated when the data on the data bus is inverted. The
bus agent will invert the data bus signals if more than half the bits, within the
covered group, would change level in the next cycle.
DBR#
Output
DBR# is used only in processor systems where no debug port is implemented on
the system board. DBR# is used by a debug port interposer so that an in-target
probe can drive system reset. If a debug port is implemented in the system, DBR#
is a no connect in the system. DBR# is not a processor signal.
the system board. DBR# is used by a debug port interposer so that an in-target
probe can drive system reset. If a debug port is implemented in the system, DBR#
is a no connect in the system. DBR# is not a processor signal.
DBSY#
Input/
Output
DBSY# (Data Bus Busy) is asserted by the agent responsible for driving data on the
processor system bus to indicate that the data bus is in use. The data bus is
released after DBSY# is deasserted. This signal must connect the appropriate pins
on all processor system bus agents.
processor system bus to indicate that the data bus is in use. The data bus is
released after DBSY# is deasserted. This signal must connect the appropriate pins
on all processor system bus agents.
DEFER#
Input
DEFER# is asserted by an agent to indicate that a transaction cannot be
guaranteed in-order completion. Assertion of DEFER# is normally the responsibility
of the addressed memory or Input/Output agent. This signal must connect the
appropriate pins of all processor system bus agents.
guaranteed in-order completion. Assertion of DEFER# is normally the responsibility
of the addressed memory or Input/Output agent. This signal must connect the
appropriate pins of all processor system bus agents.
DP[3:0]#
Input/
Output
DP[3:0]# (Data parity) provide parity protection for the D[63:0]# signals. They are
driven by the agent responsible for driving D[63:0]#, and must connect the
appropriate pins of all Pentium 4 processor system bus agents.
driven by the agent responsible for driving D[63:0]#, and must connect the
appropriate pins of all Pentium 4 processor system bus agents.
Table 32. Signal Description (Page 3 of 8)
Name
Type
Description
Quad-Pumped Signal Groups
Data Group
DSTBN#/
DSTBP#
DBI#
D[15:0]#
0
0
D[31:16]#
1
1
D[47:32]#
2
2
D[63:48]#
3
3
DBI[3:0] Assignment To Data Bus
Bus Signal
Data Bus Signals
DBI3#
D[63:48]#
DBI2#
D[47:32]#
DBI1#
D[31:16]#
DBI0#
D[15:0]#