Intel 4 1.60 GHz BX80528JK160G User Manual

                                               

   

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RESET# will cause the processor to immediately initialize itself, but the processor will stay in 
Stop-Grant state. A transition back to the Normal state will occur with the de-assertion of the 
STPCLK# signal. When re-entering the Stop Grant state from the Sleep state, STPCLK# should 
only be de-asserted one or more bus clocks after the de-assertion of SLP#.

A transition to the HALT/Grant Snoop state will occur when the processor detects a snoop on the 
system bus (see Section 7.2.4). A transition to the Sleep state (see Section 7.2.5) will occur with the 
assertion of the SLP# signal.

While in the Stop-Grant State, SMI#, INIT#, BINIT# and LINT[1:0] will be latched by the 
processor, and only serviced when the processor returns to the Normal State. Only one occurrence 
of each event will be recognized upon return to the Normal state.

While in Stop-Grant state, the processor will process a system bus snoop. 

The processor will respond to snoop transactions on the system bus while in Stop-Grant state or in 
AutoHALT Power Down state. During a snoop transaction, the processor enters the HALT/Grant 
Snoop state. The processor will stay in this state until the snoop on the system bus has been 
serviced (whether by the processor or another agent on the system bus). After the snoop is serviced, 
the processor will return to the Stop-Grant state or AutoHALT Power Down state, as appropriate.

The Sleep state is a very low power state in which the processor maintains its context, maintains 
the phase-locked loop (PLL), and has stopped all internal clocks. The Sleep state can only be 
entered from Stop-Grant state. Once in the Stop-Grant state, the processor will enter the Sleep state 
upon the assertion of the SLP# signal. The SLP# pin should only be asserted when the processor is 
in the Stop Grant state. SLP# assertions while the processor is not in the Stop Grant state is out of 
specification and may result in illegal operation. 

Snoop events that occur while in Sleep State or during a transition into or out of Sleep state will 
cause unpredictable behavior.

In the Sleep state, the processor is incapable of responding to snoop transactions or latching 
interrupt signals. No transitions or assertions of signals (with the exception of SLP# or RESET#) 
are allowed on the system bus while the processor is in Sleep state. Any transition on an input 
signal before the processor has returned to Stop-Grant state will result in unpredictable behaviour.

If RESET# is driven active while the processor is in the Sleep state, and held active as specified in 
the RESET# pin specification, then the processor will reset itself, ignoring the transition through 
Stop-Grant State. If RESET# is driven active while the processor is in the Sleep State, the SLP# 
and STPCLK# signals should be deasserted immediately after RESET# is asserted to ensure the 
processor correctly executes the Reset sequence.

While in the Sleep state, the processor is capable of entering its lowest power state, the Deep Sleep 
state, by stopping the BCLK[1:0] inputs. (See Section 7.2.6). Once in the Sleep or Deep Sleep 
states, the SLP# pin must be de-asserted if another asynchronous system bus event needs to occur. 
The SLP# pin has a minimum assertion of one BCLK period.

When the processor is in Sleep state, it will not respond to interrupts or snoop transactions.