Intel III 1.13 GHz BX80530C1133256 User Manual
Product codes
BX80530C1133256
Datasheet
25
Pentium
®
III Processor for the PGA370 Socket at 500 MHz to 1.13 GHz
2.8.2
System Bus Frequency Select Signals (BSEL[1:0])
These signals are used to select the system bus frequency for the processor. The BSEL signals are
also used by the chipset and system bus clock generator.
also used by the chipset and system bus clock generator.
Table 5
defines the possible combinations
of the signals and the frequency associated with each combination. The frequency selection is
determined by the processor(s) and driven out to the chipset and clock generator. All system bus
agents must operate at the same frequency determined by the processor. The Pentium
determined by the processor(s) and driven out to the chipset and clock generator. All system bus
agents must operate at the same frequency determined by the processor. The Pentium
III
processor for the PGA370 socket operates at 100 MHz or 133 MHz system bus frequency;
66 MHz system bus operation is not supported. Individual processors will only operate at their
specified front side bus (FSB) frequency, either 100 MHz or 133 MHz, not both. Over or under-
clocking the system bus frequency outside the specified rating marked on the package is not
recommended.
66 MHz system bus operation is not supported. Individual processors will only operate at their
specified front side bus (FSB) frequency, either 100 MHz or 133 MHz, not both. Over or under-
clocking the system bus frequency outside the specified rating marked on the package is not
recommended.
On motherboards that support operation at either 100 MHz or 133 MHz, the BSEL1 signal must be
pulled up to a logic high by a resistor located on the motherboard and provided as a frequency
selection signal to the clock driver/synthesizer. This signal can also be incorporated into RESET#
logic on the motherboard if only 133 MHz operation is supported (thus forcing the RESET# signal
to remain active as long as the BSEL1 signal is low.
pulled up to a logic high by a resistor located on the motherboard and provided as a frequency
selection signal to the clock driver/synthesizer. This signal can also be incorporated into RESET#
logic on the motherboard if only 133 MHz operation is supported (thus forcing the RESET# signal
to remain active as long as the BSEL1 signal is low.
The BSEL0 signal will float from the processor and should be pulled up to a logic high by a resistor
located on the motherboard. The BSEL0 signal can be incorporated into RESET# logic on the
motherboard if 66 MHz operation is unsupported, as demonstrated in
located on the motherboard. The BSEL0 signal can be incorporated into RESET# logic on the
motherboard if 66 MHz operation is unsupported, as demonstrated in
Figure 7
. Refer to the
appropriate clock synthesizer design guidelines and platform design guide for more details on the
bus frequency select signals.
bus frequency select signals.
In a 2-way MP system design, these BSEL[1:0] signals must connect the pins of both processors.
NOTES:
1. Some clock drivers may require a series resistor on their BSEL1 input.
2. Some chipsets may connect to the BSEL[1:0] signals and require a series resistor. See the appropriate
2. Some chipsets may connect to the BSEL[1:0] signals and require a series resistor. See the appropriate
platform design guide for implementation details.
Figure 7. BSEL[1:0] Example for a 100/133 MHz or 100 MHz Only System Design
Processor
BSEL0
BSEL1
Chipset
Clock Driver
1 K
Ω
1 K
Ω
3.3V
3.3V
10 K
Ω
Note 1
10 K
Ω
Note 2
10 K
Ω
Note 2