Intel III Xeon 900 MHz 80526KY9002M Data Sheet
Product codes
80526KY9002M
PENTIUM® III XEON™ PROCESSOR AT 600 MHz to 1 GHz with 256KB L2 Cache
ELECTRICAL SPECIFICATIONS
21
Table 9. SMBus Signal Group, DC Specifications at the processor edge fingers
Symbol
Parameter
Min
Max
Unit
Notes
V
IL
Input Low Voltage
-0.3
0.3 x
VCC_SMB
V
V
IH
Input High Voltage
0.7 x
VCC
SMB
3.465
V
3.3V + 5% maximum
V
OL
Output Low Voltage
0.4
V
I
OL
Output Low Current
3
mA
Except SMBALERT#
I
OL2
Output Low Current
6
mA
SMBALERT# 1
I
LI
Input Leakage Current
10
µA
I
LO
Output Leakage Current
10
µA
NOTES:
1.
SMBALERT# is an open drain signal.
Table 10. OCVR Control Signals, DC Specifications at the processor edge fingers
Symbol
Parameter
Min
Max
Unit
Notes
V
IL
OCVR_EN
Input Low Voltage
0.8
V
2, 3
V
IH
OCVR_EN
Input High Voltage
2.0
V
2, 3
V
OL
OCVR_OK
Output Low Voltage
0.4
V
-1.5mA max
V
OH
OCVR_OK
Output High Voltage
-
-
V
1
NOTES:
1.
Driver configured as open drain connected to 3.3V (Vcc_SMB) through a 10K ohm resistor.
2.
Vih_max (absolute) = 5.25VDC when the OCVR is powered.
3.
If the OCVR on the processor is not operating, such as at initial system power up or if there is no power input to the processor, the
input should be driven in such a way that no more than 20 mA can flow into the input (assuming it is connected to ground). This is
equivalent to using a 270-ohm or higher pull-up resistor tied to a typical 5V supply as the only source for driving the input high.
input should be driven in such a way that no more than 20 mA can flow into the input (assuming it is connected to ground). This is
equivalent to using a 270-ohm or higher pull-up resistor tied to a typical 5V supply as the only source for driving the input high.
3.11
AGTL+ System Bus Specifications
Table 11 below lists parameters controlled within the Pentium® III Xeon™ processor at 600 MHz+ to be taken into
consideration during simulation. The input buffers determine valid high and low levels by using a reference voltage
(VREF) that is generated internally on the processor cartridge from VTT. VREF should be set to the same level for other
AGTL+ logic using a voltage divider on the baseboard. It is important that the baseboard impedance be held as tight as
possible and that the intrinsic trace capacitance for the AGTL+ signal group traces is known and well-controlled. See
Layout Guidelines (section 2.4) for impedance recommendations.
consideration during simulation. The input buffers determine valid high and low levels by using a reference voltage
(VREF) that is generated internally on the processor cartridge from VTT. VREF should be set to the same level for other
AGTL+ logic using a voltage divider on the baseboard. It is important that the baseboard impedance be held as tight as
possible and that the intrinsic trace capacitance for the AGTL+ signal group traces is known and well-controlled. See
Layout Guidelines (section 2.4) for impedance recommendations.