Intel III Xeon 900 MHz 80526KY9002M Data Sheet
Product codes
80526KY9002M
PENTIUM® III XEON™ PROCESSOR AT 600 MHz to 1 GHz with 256KB L2 Cache
SIGNAL QUALITY
31
4. SIGNAL QUALITY
Signals driven on the Pentium® III Xeon™ processor at 600 MHz+ system bus should meet signal quality specifications
to ensure that the components read data properly and to ensure that incoming signals do not affect the long-term
reliability of the component. Specifications are provided for simulation at the processor core. Meeting the specifications at
the processor core in Table 20 through Table 25 ensures that signal quality effects will not adversely affect processor
operation.
to ensure that the components read data properly and to ensure that incoming signals do not affect the long-term
reliability of the component. Specifications are provided for simulation at the processor core. Meeting the specifications at
the processor core in Table 20 through Table 25 ensures that signal quality effects will not adversely affect processor
operation.
4.1 Bus Clock Signal Quality Specifications
Table 20 describes the signal quality specifications at the processor core pad for the Pentium III Xeon processor at 600
MHz+ system bus clock (BCLK) signal. Figure 11 shows the signal quality waveform for the system bus clock at the
processor core pads.
MHz+ system bus clock (BCLK) signal. Figure 11 shows the signal quality waveform for the system bus clock at the
processor core pads.
Table 20. BCLK Signal Quality Specifications for Simulation at the processor Core
1
V#
Parameter
Min
Nom
Max
Unit
Figure
Notes
V1:
BCLK V
IL
-0.3
0.5
V
11
V2:
BCLK V
IH
2.0
2.625
V
11
V3:
V
IN
Absolute Voltage Range
–0.7
2.0
3.3
V
11
V4:
Rising Edge Ringback
2.0
V
11
2
V5:
Falling Edge Ringback
0.5
V
11
2
NOTES:
1.
Unless otherwise noted, all specifications in this table apply to all Pentium III Xeon processor at 600 MHz+ frequencies.
2.
The rising and falling edge ringback voltage specified is the minimum (rising) or maximum (falling) absolute voltage the BCLK signal
can dip back to after passing the V
can dip back to after passing the V
IH
(rising) or V
IL
(falling) voltage limits. This specification is an absolute value.
V2
V1
V3
V3
T3
V5
V4
T6
T4
T5
000806
Figure 11. BCLK, TCK, PICCLK Generic Clock Waveform at the processor Core Pins
4.2
AGTL+ Signal Quality Specifications
Refer to the Pentium II processor Developer's Manual (Order Number 243341) for the specification for AGTL+.