Intel 4 620 JM80547PG0722MM Data Sheet
Product codes
JM80547PG0722MM
12
Datasheet
Introduction
bus can deliver addresses two times per bus clock and is referred to as a “double-clocked” or 2X
address bus. Working together, the 4X data bus and 2X address bus provide a data bus bandwidth
of up to 6.4 GB/s (800 MHz FSB) or 8.5 GB/s (1066 MHz FSB).
address bus. Working together, the 4X data bus and 2X address bus provide a data bus bandwidth
of up to 6.4 GB/s (800 MHz FSB) or 8.5 GB/s (1066 MHz FSB).
The Pentium 4 processor includes the Execute Disable Bit capability previously available in Intel
®
Itanium
®
processors. This feature, combined with a supported operating system, allows memory to
be marked as executable or non-executable. If code attempts to run in non-executable memory the
processor raises an error to the operating system. This feature can prevent some classes of viruses
or worms that exploit buffer over run vulnerabilities and can thus help improve the overall security
of the system. See the Intel
processor raises an error to the operating system. This feature can prevent some classes of viruses
or worms that exploit buffer over run vulnerabilities and can thus help improve the overall security
of the system. See the Intel
®
Architecture Software Developer's Manual for more detailed
information.
The Pentium 4 processor 662 and 672 support Intel
®
Virtualization Technology. Intel Virtualization
Technology provides silicon-based functionality that works together with compatible Virtual
Machine Monitor (VMM) software to improve upon software-only solutions. Because this
virtualization hardware provides a new architecture upon which the operating system can run
directly, it removes the need for binary translation. Thus, it helps eliminate associated performance
overhead and vastly simplifies the design of the VMM, in turn allowing VMMs to be written to
common standards and to be more robust. See the Intel
Machine Monitor (VMM) software to improve upon software-only solutions. Because this
virtualization hardware provides a new architecture upon which the operating system can run
directly, it removes the need for binary translation. Thus, it helps eliminate associated performance
overhead and vastly simplifies the design of the VMM, in turn allowing VMMs to be written to
common standards and to be more robust. See the Intel
®
Virtualization Technology Specification
for the IA-32 Intel
®
Architecture for more details.
The Pentium 4 processor 6xx sequence features Enhanced Intel SpeedStep
®
technology. Enhanced
Intel SpeedStep technology allows trade-offs to be made between performance and power
consumptions. This may lower average power consumption (in conjunction with OS support). The
Pentium 4 processor Extreme Edition does not support Enhanced Intel SpeedStep technology.
consumptions. This may lower average power consumption (in conjunction with OS support). The
Pentium 4 processor Extreme Edition does not support Enhanced Intel SpeedStep technology.
Intel will enable support components for the processor including heatsink, heatsink retention
mechanism, and socket. Manufacturability is a high priority; hence, mechanical assembly may be
completed from the top of the baseboard and should not require any special tooling.
mechanism, and socket. Manufacturability is a high priority; hence, mechanical assembly may be
completed from the top of the baseboard and should not require any special tooling.
The processor includes an address bus powerdown capability that removes power from the address
and data pins when the FSB is not in use. This feature is always enabled on the processor.
and data pins when the FSB is not in use. This feature is always enabled on the processor.
1.1
Terminology
A ‘#’ symbol after a signal name refers to an active low signal, indicating a signal is in the active
state when driven to a low level. For example, when RESET# is low, a reset has been requested.
Conversely, when NMI is high, a nonmaskable interrupt has occurred. In the case of signals where
the name does not imply an active state but describes part of a binary sequence (such as address or
data), the ‘#’ symbol implies that the signal is inverted. For example, D[3:0] = ‘HLHL’ refers to a
hex ‘A’, and D[3:0]# = ‘LHLH’ also refers to a hex ‘A’ (H= High logic level, L= Low logic level).
state when driven to a low level. For example, when RESET# is low, a reset has been requested.
Conversely, when NMI is high, a nonmaskable interrupt has occurred. In the case of signals where
the name does not imply an active state but describes part of a binary sequence (such as address or
data), the ‘#’ symbol implies that the signal is inverted. For example, D[3:0] = ‘HLHL’ refers to a
hex ‘A’, and D[3:0]# = ‘LHLH’ also refers to a hex ‘A’ (H= High logic level, L= Low logic level).
“FSB” refers to the interface between the processor and system core logic (a.k.a. the chipset
components). The FSB is a multiprocessing interface to processors, memory, and I/O.
components). The FSB is a multiprocessing interface to processors, memory, and I/O.