Intel 4 620 JM80547PG0722MM Data Sheet

22

.

Legacy input signals (such as, A20M#, IGNNE#, INIT#, SMI#, and STPCLK#) use CMOS input 
buffers. All of these signals follow the same DC requirements as GTL+ signals; however, the 
outputs are not actively driven high (during a logical 0-to-1 transition) by the processor. These 
signals do not have setup or hold time specifications in relation to BCLK[1:0].

All of the GTL+ Asynchronous signals are required to be asserted/de-asserteded for at least six 
BCLKs for the processor to recognize the proper signal state. See 

 through 

 for the DC specifications for the GTL+ Asynchronous signal groups. See 

 

for additional timing requirements for entering and leaving the low power states.

Due to the voltage levels supported by other components in the Test Access Port (TAP) logic, it is 
recommended that the Pentium 4 processor be first in the TAP chain and followed by any other 
components within the system. A translation buffer should be used to connect to the rest of the 
chain unless one of the other components is capable of accepting an input of the appropriate 
voltage level. Similar considerations must be made for TCK, TMS, TRST#, TDI, and TDO. Two 
copies of each signal may be required, with each driving a different voltage level.

A[35:3]#, ADS#, ADSTB[1:0]#, AP[1:0]#, BINIT#, 
BNR#, BOOTSELECT

1

, BPRI#, D[63:0]#, DBI[3:0]#, 

DBSY#, DEFER#, DP[3:0]#, DRDY#, DSTBN[3:0]#, 
DSTBP[3:0]#, HIT#, HITM#, LOCK#, MCERR#, 
PROCHOT#, REQ[4:0]#, RS[2:0]#, RSP#, TRDY#

1.

The BOOTSELECT signal has a 500–5000 

Ω pull-up to V

TT

 rather than on-die termination.

A20M#, BCLK[1:0], BPM[5:0]#, BR0#, BSEL[2:0], 
COMP[1:0], FERR#/PBE#, IERR#, IGNNE#, INIT#, 
LINT0/INTR, LINT1/NMI, PWRGOOD, RESET#, 
SKTOCC#, SMI#, STPCLK#, TDO, TESTHI[13:0], 
THERMDA, THERMDC, THERMTRIP#, VID[5:0], 
VTTPWRGD, GTLREF, TCK, TDI, TRST#, TMS

2.

Signals that do not have R

TT

, nor are actively driven to their high-voltage level.

BSEL[2:0], VID[5:0], THERMTRIP#, FERR#/PBE#, 
IERR#, BPM[5:0]#, BR0#, TDO, VTT_SEL, LL_ID[1:0], 
MSID[1:0]

BPM[5:0]#, LINT0/INTR, LINT1/NMI, RESET#, BINIT#, 
BNR#, HIT#, HITM#, MCERR#, PROCHOT#, BR0#, 
A[35:0]#, ADS#, ADSTB[1:0]#, AP[1:0]#, BPRI#, D[63:0]#, 
DBI[3:0]#, DBSY#, DEFER#, DP[3:0]#, DRDY#, 
DSTBN[3:0]#, DSTBP[3:0]#, LOCK#, REQ[4:0]#, RS[2:0]#, 
RSP#, TRDY#

BOOTSELECT, VTTPWRGD, A20M#, 
IGNNE#, INIT#, PWRGOOD

STPCLK#, TCK

1

, TDI

, TRST#

1.

These signals also have hysteresis added to the reference voltage. See 

 for more information.