Intel 900 MHz RK80530RY900256 Data Sheet
Product codes
RK80530RY900256
Mobile Intel
®
Celeron
®
Processor (0.18µ) in BGA2 and Micro-PGA2 Packages
283654-003 Datasheet
27
Table 12. Clock, APIC, TAP, CMOS, and Open-drain Signal Group DC Specifications
T
J
= 0°C to 100°C; T
J
= 5°C to 100°C for Vcc = 1.15V; V
CC
= 1.10V ±80 mV or 1.15V ±80 mV or 1.35V ±100
mV or 1.60V ±115; V
CCT
= 1.50V ±115 mV
Symbol Parameter
Min
Max
Unit Notes
V
IL15
Input Low Voltage, 1.5V CMOS
–0.15
V
CMOSREFmin
–
200 mV
V
V
IL25
Input Low Voltage, 2.5V CMOS
–0.3
0.7
V
Notes 1, 2
V
IL33
Input Low Voltage, 3.3V CMOS
–0.15
V
CMOSREFmin
–
200 mV
V Note
7
V
IL,BCLK
Input Low Voltage, BCLK
–0.3
0.5
V
Note 2
V
IH15
Input High Voltage, 1.5V CMOS
V
CMOSREFmax
+
200 mV
V
CCT
V
V
IH25
Input High Voltage, 2.5V CMOS
2.0
2.625
V
Notes 1, 2
V
IH33
Input High Voltage, 3.3V CMOS
V
CMOSREFmax
+
200 mV
3.465 V
Note
7
V
IH,BCLK
Input High Voltage, BCLK
2.0
2.625
V
Note 2
V
OL
Output
Low
Voltage
0.4
V
Note
3
V
OH15
Output High Voltage, 1.5V CMOS
N/A
1.615
V
All outputs are Open-
drain
drain
V
OH25
Output High Voltage, 2.5V CMOS
N/A
2.625
V
All outputs are Open-
drain
drain
V
OH,VID
Output High Voltage, VID ball/pins N/A
5.50
V
5V + 10%
V
CMOSREF
CMOSREF Voltage
0.90
1.10
V
Note 4
V
CLKREF
CLKREF Voltage
1.175
1.325
V
1.25V ±6%, Note 4
I
OL
Output Low Current
10
mA
Note 6
I
L
Leakage Current for Inputs,
Outputs and I/Os
Outputs and I/Os
±100
µ
A
Notes 5,8
NOTES:
1.
Parameter applies to the PICCLK and PWRGOOD signals only.
2.
VILx,min and VIHx,max only apply when BCLK and PICCLK are stopped. BCLK and PICCLK should be
stopped in the low state. See Table 22 for the BCLK voltage range specifications for when BCLK is
running. See Table 23 for the PICCLK voltage range specifications for when PICCLK is running.
stopped in the low state. See Table 22 for the BCLK voltage range specifications for when BCLK is
running. See Table 23 for the PICCLK voltage range specifications for when PICCLK is running.
3.
Parameter measured at 10 mA.
4.
V
CMOSREF
and V
CLKREF
should be created from a stable voltage supply using a voltage divider.
5.
(0
≤
V
IN/OUT
≤
V
IHx,max
).
6.
Specified as the minimum amount of current that the output buffer must be able to sink. However, V
OL,max
cannot be guaranteed if this specification is exceeded.
7.
Parameter applies to BSEL[1:0] signals only.
8.
For BSEL[1:0] signals, I
L,Max
can be up to 100
µ
A (with1 K
Ω
pull-up to1.5V) and up to 500
µ
A (with 1 K
Ω
pull-up to 3.3V).