Intel L2400 LE80539LF0282M User Manual

Datasheet

17

Dynamic Cache Sizing allows the processor to flush and disable a programmable 

number of L2 cache ways upon each Deeper Sleep entry under the following 

conditions:

• The second core is already in C4 and the Intel Enhanced Deeper Sleep state is 

enabled (as specified in 

• The C0 timer, which tracks continuous residency in the Normal package state, has 

not expired. This timer is cleared during the first entry into Deeper Sleep to allow 

consecutive Deeper Sleep entries to shrink the L2 cache as needed. 

• The FSB speed to processor core speed ratio is below the predefined L2 shrink 

threshold. 

If the FSB speed to processor core speed ratio is above the predefined L2 shrink 

threshold, then L2 cache expansion will be requested. If the ratio is zero, then the ratio 

will not be taken into account for Dynamic Cache Sizing decisions. 

Upon STPCLK# deassertion, the first core exiting the Intel Enhanced Deeper Sleep 

state will expand the L2 cache to 2 ways and invalidate previously disabled cache ways. 

If the L2 cache reduction conditions stated above still exist when the last core returns 

to C4 and the package enters Intel Enhanced Deeper Sleep state, then the L2 will be 

shrunk to zero again. If a core requests a processor performance state resulting in a 

higher ratio than the predefined L2 shrink threshold, the C0 timer expires, or the 

second core (not the one currently entering the interrupt routine) requests the C1, C2, 

or C3 states, then the whole L2 will be expanded when the next INTR event would 

occur.

L2 cache shrink prevention may be enabled as needed on occasion through an 

MWAIT(C4) sub-state field. If shrink prevention is enabled, then the processor does not 

enter the Intel Enhanced Deeper Sleep state since the L2 cache remains valid and in 

full size.

Intel Core Duo processor and Intel Core Solo processor feature Enhanced Intel 

SpeedStep Technology. Following are the key features of Enhanced Intel SpeedStep 

Technology:

• Multiple voltage/frequency operating points provide optimal performance at the 

lowest power. 

• Voltage/Frequency selection is software controlled by writing to processor MSR’s 

(Model Specific Registers).

— If the target frequency is higher than the current frequency, V

CC

 is ramped up 

in steps by placing new values on the VID pins and the PLL then locks to the 

new frequency.

— If the target frequency is lower than the current frequency, the PLL locks to the 

new frequency and the V

CC

 is changed through the VID pin mechanism.

— Software transitions are accepted at any time. If a previous transition is in 

progress, the new transition is deferred until the previous transition completes.

• The processor controls voltage ramp rates internally to ensure glitch free 

transitions.

• Low transition latency and large number of transitions possible per second.

— Processor core (including L2 cache) is unavailable for up to 10 μs during the 

frequency transition