Intel 1.40 GHz RH80532NC017256 Data Sheet

298517-006 Datasheet 

11 

•  On-die second level (L2) cache 

—  8-way set associative, 32-byte line size, 1 line per sector 
—  Operates at full core speed 
—  256-Kbyte ECC protected cache data array 

•  AGTL system bus interface 

—  64-bit data bus, 100-MHz and 133-MHz operation 
—  Uniprocessor, two loads only (processor and chipset) 
—  Integrated termination 

•  Processor clock control 

—  Quick Start for low power, low exit latency clock “throttling” 
—  Deep Sleep mode for lower power dissipation 

•  Thermal diode for measuring processor temperature 

All information in this document is the best available information at the time of publication.  Revisions 
of this document will be provided on an as-required basis until the Mobile Intel Celeron Processor is 
released for production orders. 

# 

A “#” symbol following a signal name indicates that the signal is active low. This means that when the signal 
is asserted (based on the name of the signal) it is in an electrical low state. Otherwise, signals are driven in 
an electrical high state when they are asserted. In state machine diagrams, a signal name in a condition 
indicates the condition of that signal being asserted 

! 

Indicates the condition of that signal not being asserted. For example, the condition “!STPCLK# and HS” is 
equivalent to “the active low signal STPCLK# is unasserted (i.e., it is at 1.5V) and the HS condition is true.” 

L 

Electrical low signal levels 

H 

Electrical high signal levels 

0 

Logical low.  For example, BD[3:0] = “1010” = “HLHL” refers to a hexadecimal “A,” and D[3:0]# = “1010” = 
“LHLH” also refers to a hexadecimal “A.” 

1 

Logical high. For example, BD[3:0] = “1010” = “HLHL” refers to a hexadecimal “A,” and D[3:0]# = “1010” = 
“LHLH” also refers to a hexadecimal “A.” 

TBD 

Specifications that are yet to be determined and will be updated in future revisions of the document. 

X 

Don’t care condition