Intel 1.40 GHz RH80532NC017256 Data Sheet

298517-006 Datasheet 

5 

Figure 1. Clock Control States................................................................................................. 15

 

Figure 2. PLL RLC Filter.......................................................................................................... 23

 

Figure 3. VTTPWRGD System-Level Connections................................................................. 24

 

Figure 4. Noise Estimation ...................................................................................................... 25

 

Figure 5. Illustration of V

CC

 Static and Transient Tolerances (VID  = 1.15 V) ......................... 37

 

Figure 6. Illustration of Deep Sleep V

CC

 Static and Transient Tolerances (VID  

Setting = 1.15 V) ...................................................................................................... 37

 

Figure 7. Illustration of V

CC

 Static and Transient Tolerances (VID  = 1.40 V) ......................... 38

 

Figure 8. Illustration of Deep Sleep V

CC

 Static and Transient Tolerances (VID 

Setting = 1.40 V) ...................................................................................................... 39

 

Figure 9. BCLK (Single Ended)/PICCLK/TCK Generic Clock Timing Waveform.................... 49

 

Figure 10. Differential BCLK/BCLK# Waveform (Common Mode).......................................... 49

 

Figure 11. BCLK/BCLK# Waveform (Differential Mode) ......................................................... 50

 

Figure 12. Valid Delay Timings................................................................................................ 50

 

Figure 13.

 

 Setup and Hold Timings......................................................................................... 51

 

Figure 14. Cold/Warm Reset and Configuration Timings........................................................ 51

 

Figure 15. Power-on Sequence and Reset Timings................................................................ 52

 

Figure 16. Power Down Sequencing and Timings (VCC Leading) ......................................... 53

 

Figure 17.

 

Power Down Sequencing and Timings (V

CCT

 Leading)........................................... 54

 

Figure 18.

 

Test Timings (Boundary Scan)................................................................................ 55

 

Figure 19. Test Reset Timings ................................................................................................ 55

 

Figure 20.

 

Quick Start/Deep Sleep Timing (BCLK Stopping Method)...................................... 56

 

Figure 21. Quick Start/Deep Sleep Timing (DPSLP# Assertion Method) ............................... 57

 

Figure 22. BCLK (Single Ended)/PICCLK Generic Clock Waveform...................................... 59

 

Figure 23. Maximum Acceptable Overshoot/Undershoot Waveform ...................................... 60

 

Figure 24. VTTPWRGD Noise Specification ........................................................................... 64

 

Figure 25. Socketable Micro-FCPGA Package - Top and Bottom Isometric Views................ 66

 

Figure 26. Socketable Micro-FCPGA Package - Top and Side View ..................................... 67

 

Figure 27. Socketable Micro-FCPGA Package - Bottom View ............................................... 68

 

Figure 28. Micro-FCBGA Package – Top and Bottom Isometric Views.................................. 70

 

Figure 29. Micro-FCBGA Package – Top and Side Views...................................................... 71

 

Figure 30. Micro-FCBGA Package - Bottom View .................................................................. 72

 

Figure 31. Pin/Ball Map - Top View ......................................................................................... 73

 

Figure 32. PLL Filter Specifications......................................................................................... 97