Intel 1.40 GHz RH80532NC017256 Data Sheet
Product codes
RH80532NC017256
Mobile Intel
®
Celeron
®
Processor (0.13 µ)
Micro-FCBGA and Micro-FCPGA Packages Datasheet
298517-006 Datasheet
51
Figure 13. Setup and Hold Timings
CLK
Signal
V Valid
T
h
Ts
D0005-00
Vc
NOTES:
T
s
= T8, T27 (Setup Time)
T
h
= T9, T28 (Hold Time)
V = V
REF
for AGTL signals; 1.0V for CMOS, APIC, and TAP signals
Vc = Crossing point of BCLK rising edge and BCLK# falling edge for BCLK references (Differential Clock)
= 1.25V (Single Ended Clock)
Figure 14. Cold/Warm Reset and Configuration Timings
BCLK
RESET#
T
v
T
x
T
t
T
u
V
C
V
D0006-02
Configuration
(A[15:5], BREQ0#,
FLUSH#, INIT#,
PICD0)
T
w
Valid
PICD[1:0]
AGTL/non-AGTL
outputs
Non-configuration
inputs
T
y
Valid
T
z
Active
NOTES:
T
t
= T9 (AGTL Input Hold Time)
T
u
= T8 (AGTL Input Setup Time)
T
v
= T10 (RESET# Pulse Width)
T
w
= T16 (Reset Configuration Signals (A[15:5]#, BREQ0#, FLUSH#, INIT#, PICD0) Setup Time)
T
x
= T17 (Reset Configuration Signals (A[15:5]#, BREQ0#, FLUSH#, INIT#, PICD0) Hold Time)
T
y
= T18D (RESET# inactive to Valid Outputs)
T
z
= T18E (RESET# inactive to Drive Signals)
Vc= Crossing point of BCLK rising edge and BCLK# falling edge (Differential Clock)
= 1.25 V (Single Ended Clock)