Intel 850 MHz KC80526NY850128 Data Sheet
Product codes
KC80526NY850128
R
Mobile Intel® Celeron® Processor Specification Update
27
M4.
Double ECC Error on Read May Result in BINIT#
Problem:
For this erratum to occur, the following conditions must be met:
• Machine Check Exceptions (MCEs) must be enabled.
• A dataless transaction (such as a write invalidate) must be occurring simultaneously with a
transaction which returns data (a normal read).
• The read data must contain a double-bit uncorrectable ECC error.
If these conditions are met, the mobile processor will not be able to determine which transaction was
erroneous, and instead of generating an MCE, it will generate a BINIT#.
erroneous, and instead of generating an MCE, it will generate a BINIT#.
Implication:
The bus will be reinitialized in this case. However, since a double-bit uncorrectable ECC error occurred
on the read, the MCE handler (which is normally reached on a double-bit uncorrectable ECC error for a
read) would most likely cause the same BINIT# event.
on the read, the MCE handler (which is normally reached on a double-bit uncorrectable ECC error for a
read) would most likely cause the same BINIT# event.
Workaround:
Though the ability to drive BINIT# can be disabled in the mobile processor, which would prevent the
effects of this erratum, overall system behavior would not improve, since the error which would
normally cause a BINIT# would instead cause the machine to shut down. No other workaround has been
identified.
effects of this erratum, overall system behavior would not improve, since the error which would
normally cause a BINIT# would instead cause the machine to shut down. No other workaround has been
identified.
Status:
For the steppings affected see the Summary of Changes at the beginning of this section.
M5.
FP Inexact-Result Exception Flag May Not Be Set
Problem:
When the result of a floating-point operation is not exactly representable in the destination format (1/3 in
binary form, for example), an inexact-result (precision) exception occurs. When this occurs, the PE bit
(bit 5 of the FPU status word) is normally set by the processor. Under certain rare conditions, this bit
may not be set when this rounding occurs. However, other actions taken by the processor (invoking the
software exception handler if the exception is unmasked) are not affected. This erratum can only occur if
the floating-point operation which causes the precision exception is immediately followed by one of the
following instructions:
binary form, for example), an inexact-result (precision) exception occurs. When this occurs, the PE bit
(bit 5 of the FPU status word) is normally set by the processor. Under certain rare conditions, this bit
may not be set when this rounding occurs. However, other actions taken by the processor (invoking the
software exception handler if the exception is unmasked) are not affected. This erratum can only occur if
the floating-point operation which causes the precision exception is immediately followed by one of the
following instructions:
• FST m32real
• FST m64real
• FSTP m32real
• FSTP m64real
• FSTP m80real
• FIST m16int
• FIST m32int
• FISTP m16int
• FISTP m32int
• FISTP m64int
Note that even if this combination of instructions is encountered, there is also a dependency on the
internal pipelining and execution state of both instructions in the processor.
internal pipelining and execution state of both instructions in the processor.