Intel 850 MHz KC80526NY850128 Data Sheet
Product codes
KC80526NY850128
R
Mobile Intel® Celeron® Processor Specification Update
57
M90.
Values for LBR/BTS/BTM will be Incorrect after an Exit from SMM
Problem:
After a return from SMM (System Management Mode), the CPU will incorrectly update the LBR (Last
Branch Record) and the BTS (Branch Trace Store), hence rendering their data invalid. The
corresponding data if sent out as a BTM on the system bus will also be incorrect.
Branch Record) and the BTS (Branch Trace Store), hence rendering their data invalid. The
corresponding data if sent out as a BTM on the system bus will also be incorrect.
Note: This issue would only occur when one of the 3 above mentioned debug support facilities are used.
Implication:
The value of the LBR, BTS, and BTM immediately after an RSM operation should not be used.
Workaround:
None identified.
Status:
For the steppings affected, see the Summary Tables of Changes.
M91. INIT Does Not Clear Global Entries in the TLB
Problem:
INIT may not flush a TLB entry when:
1. The processor is in protected mode with paging enabled and the page global enable flag is set
(PGE bit of CR4 register)
(PGE bit of CR4 register)
2. G bit for the page table entry is set
3. TLB entry is present in TLB when INIT occurs.
Implication:
Software may encounter unexpected page fault or incorrect address translation due to a TLB entry
erroneously left in TLB after INIT.
erroneously left in TLB after INIT.
Workaround:
Write to CR3, CR4 (setting bits PSE, PGE or PAE) or CR0 (setting bits PG or PE) registers before
writing to memory early in BIOS code to clear all the global entries from TLB.
writing to memory early in BIOS code to clear all the global entries from TLB.
Status:
For the steppings affected, see the Summary Table of Changes.
M92. REP MOVS/STOS Executing with Fast Strings Enabled and Crossing Page
Boundaries with Inconsistent Memory Types may use an Incorrect Data Size or Lead to
Memory-Ordering Violations
Boundaries with Inconsistent Memory Types may use an Incorrect Data Size or Lead to
Memory-Ordering Violations
Problem:
Under certain conditions as described in the Software Developers Manual section “Out-of-Order Stores
For String Operations in Pentium 4, Intel Xeon, and P6 Family Processors” the processor performs REP
MOVS or REP STOS as fast strings. Due to this erratum fast string REP MOVS/REP STOS instructions
that cross page boundaries from WB/WC memory types to UC/WP/WT memory types, may start using
an incorrect data size or may observe memory ordering violations.
For String Operations in Pentium 4, Intel Xeon, and P6 Family Processors” the processor performs REP
MOVS or REP STOS as fast strings. Due to this erratum fast string REP MOVS/REP STOS instructions
that cross page boundaries from WB/WC memory types to UC/WP/WT memory types, may start using
an incorrect data size or may observe memory ordering violations.
Implication:
Upon crossing the page boundary the following may occur, dependent on the new page memory type:
• UC the data size of each write will now always be 8 bytes, as opposed to the original data size.
• WP the data size of each write will now always be 8 bytes, as opposed to the original data size and
there may be a memory ordering violation.
• WT there may be a memory ordering violation.
Workaround:
Software should avoid crossing page boundaries from WB or WC memory type to UC, WP or WT
memory type within a single REP MOVS or REP STOS instruction that will execute with fast strings
enabled.
memory type within a single REP MOVS or REP STOS instruction that will execute with fast strings
enabled.