Intel L2300 LE80539LF0212M User Manual

18

Datasheet

— The bus protocol (BNR# mechanism) is used to block snooping

• Improved Intel® Thermal Monitor mode.

— When the on-die thermal sensor indicates that the die temperature is too high, 

the processor can automatically perform a transition to a lower frequency/

voltage specified in a software programmable MSR.

— The processor waits for a fixed time period. If the die temperature is down to 

acceptable levels, an up transition to the previous frequency/voltage point 

occurs.

— An interrupt is generated for the up and down Intel Thermal Monitor transitions 

enabling better system level thermal management. 

• Enhanced thermal management features.

— Digital thermal sensor and thermal interrupts
— TM1 in addition to TM2 in case of non successful TM2 transition.
— dual core thermal management synchronization. 

Each core in the Intel Core Duo processor implements an independent MSR for 

controlling Enhanced Intel SpeedStep Technology, but both cores must operate at the 

same frequency and voltage. The processor has performance state coordination logic to 

resolve frequency and voltage requests from the two cores into a single frequency and 

voltage request for the package as a whole. If both cores request the same frequency 

and voltage then the Intel Core Duo processor will transition to the requested common 

frequency and voltage. If the two cores have different frequency and voltage requests 

then the Intel Core Duo processor will take the highest of the two frequencies and 

voltages as the resolved request and transition to that frequency and voltage.

The Extended low power states (C1E, C2E, C3E, C4E) optimize for power by forcibly 

reducing the performance state of the processor when it enters a package low power 

state. Instead of directly transitioning into the package low power states, the extended 

low power state first reduces the performance state of the processor by performing an 

Enhanced Intel SpeedStep Technology transition down to the lowest operating point. 

Upon receiving a break event from the package low power state, control will be 

returned to software while an Enhanced Intel SpeedStep Technology transition up to 

the initial operating point occurs. The advantage of this feature is that it significantly 

reduces leakage while in the package low power states.

The processor implements two software interfaces for requesting extended low power 

states: MWAIT instruction extensions with sub-state hints and via BIOS by configuring 

a software programmable MSR bit to automatically promote package low power states 

to extended low power states. 

C2E and C4E must be enabled via the BIOS for the processor to remain within 

specification.

Enhanced Intel SpeedStep Technology transitions are multistep processes that require 

clocked control. These transitions cannot occur when the processor is in the Sleep or 

Deep Sleep package low power states since processor clocks are not active in these 

states. C4E is an exception to this rule when the Hard C4E configuration is enabled in a 

software programmable MSR bit. This C4E low power state configuration will lower core 

voltage to the Deeper Sleep level while in Deeper Sleep and, upon exit, will 

automatically transition to the lowest operating voltage and frequency to reduce snoop 

service latency. The transition to the lowest operating point or back to the original 

software requested point may not be instantaneous. Furthermore, upon very frequent 

transitions between active and idle states, the transitions may lag behind the idle state