Intel 1.70 GHz RH80532NC029256 Data Sheet

298517-006 Datasheet 

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The Mobile Intel Celeron Processor uses Assisted GTL (AGTL) signaling on the PSB interface.  The 
main difference between AGTL and GTL+ used on previous Intel processors is V

CCT

 = 1.25 V for AGTL 

versus 1.5 V for GTL+.  The lower voltage swing enables high performance at lower power.   The Low 
Voltage and Ultra Low Voltage Mobile Celeron Processors will also support a 100-MHz PSB. 

The 256-K on die integrated L2 cache on the Mobile Intel Celeron Processor is double the L2 cache size 
on the Mobile Intel Celeron Processor (0.18 µ).  The L2 cache runs at the processor core speed and the 
increased cache size provides superior processing power.

  

The Mobile Intel Celeron Processor features Data Prefetch Logic that speculatively fetches data to the 
L2 cache before an L1 cache request occurs.  This reduces transactions between the cache and system 
memory reducing or eliminating bus cycle penalties, resulting in improved performance.  The processor 
also includes extensions to memory order and reorder buffers that boost performance.

 

Differential clocking requires the use of two complementary clocks: BCLK and BCLK#.  Benefits of 
differential clocking include easier scaling to lower voltages, reduced EMI, and less jitter.  All references 
to BCLK in this document apply to BCLK# also even if not explicitly stated.  The Mobile Intel Celeron 
Processor will also support Single Ended Clocking. The processor will configure itself for Differential or 
Single Ended Clocking based on the waveforms detected on the BCLK and BCLK#/CLKREF signal 
lines.