Intel 1.70 GHz RH80532NC029256 Data Sheet
Product codes
RH80532NC029256
Mobile Intel
®
Celeron
®
Processor (0.13 µ)
Micro-FCBGA and Micro-FCPGA Packages Datasheet
298517-006 Datasheet
47
Table 32. APIC Bus Signal AC Specifications
1
Symbol Parameter Min
Max
Unit
Figure
Notes
T21
PICCLK Frequency
2
33.3
MHz
Note 2
T22 PICCLK
Period
30 500 ns
6
T23
PICCLK High Time
10.5
ns
6
at>1.6 V
T24
PICCLK Low Time
10.5
ns
6
at<0.4 V
T25
PICCLK Rise Time
0.25
3.0
ns
6
(0.4 V – 1.6 V)
T26
PICCLK Fall Time
0.25
3.0
ns
6
(1.6 V – 0.4 V)
T27
PICD[1:0] Setup Time
8.0
ns
9
Note 3
T28
PICD[1:0] Hold Time
2.5
ns
9
Note 3
T29
PICD[1:0] Valid Delay (Rising
Edge)
PICD[1:0] Valid Delay (Falling
Edge)
Edge)
PICD[1:0] Valid Delay (Falling
Edge)
1.5
1.5
1.5
8.7
12.0
12.0
ns
8
Notes 3, 4
NOTES:
1. All AC timings for APIC signals are referenced to the PICCLK rising edge at 1.0 V. All CMOS signals are
referenced at 1.0 V.
2. The minimum frequency is 2 MHz when PICD0 is at 1.5 V at reset Referenced to PICCLK Rising Edge.
3. For Open-drain signals, Valid Delay is synonymous with Float Delay.
4. Valid delay timings for these signals are specified into 150
3. For Open-drain signals, Valid Delay is synonymous with Float Delay.
4. Valid delay timings for these signals are specified into 150
Ω to 1.5 V and 0 pF of external load. For real system
timings these specifications must be derated for external capacitance at 105 ps/pF.