Intel 1.70 GHz RH80532NC029256 Data Sheet

96 Datasheet

 

298517-006 

All Mobile Intel Celeron Processors have internal PLL clock generators, which are analog in nature and 
require quiet power supplies for minimum jitter.  Jitter is detrimental to a system; it degrades external 
I/O timings as well as internal core timings (i.e. maximum frequency). The PLL RLC filter 
specifications for the Mobile Intel Celeron Processor are the same as those for the mobile Intel Pentium 
III Processor-M. The general desired topology is shown in Figure 2. Excluded from the external circuitry 
are parasitics associated with each component.  

The function of the filter is two fold.  It protects the PLL from external noise through low-pass 
attenuation.  It also protects the PLL from internal noise through high-pass filtering.  In general, the low-
pass description forms an adequate description for the filter. 

The AC low-pass specification, with input at V

CCT

 and output measured across the capacitor, is as 

follows: 

•  < 0.2-dB gain in pass band 
•  < 0.5-dB attenuation in pass band < 1 Hz (see DC drop in next set of requirements) 
•  34-dB attenuation from 1 MHz to 66 MHz 
•  28-dB attenuation from 66 MHz to core frequency 
•  The filter specification (AC) is graphically shown in Figure 32. 

Other requirements: 

•  Use a shielded type inductor to minimize magnetic pickup 
•  The filter should support a DC current of at least 30 mA 

•  The DC voltage drop from V

CCT

 to PLL1 should be less than 60 mV, which in practice implies 

series resistance of less than 2 

Ω. This also means that the pass band (from DC to 1 Hz) 

attenuation below 0.43 dB for V

CCT

 = 1.25 V.