Intel 733 MHz RH80533NZ733128 Data Sheet
Product codes
RH80533NZ733128
Mobile Intel
®
Celeron
®
Processor (0.18µ) in BGA2 and Micro-PGA2 Packages
283654-003 Datasheet
39
Figure 14. Stop Grant/Sleep/Deep Sleep Timing
T
u
stpgnt
Running
BCLK
STPCLK#
CPU bus
SLP#
Compatibility
Signals
Frozen
Changing
Normal
Stop
Grant
Sleep
Deep Sleep
Sleep
Stop
Grant
Normal
Running
T
t
T
v
T
y
T
z
T
w
T
x
V0011-00
Changing
NOTES
:
T
t
= T50 (Stop Grant Acknowledge Bus Cycle Completion to SLP# Assertion Delay)
T
u
= T51 (Setup Time to Input Signal Hold Requirement)
T
v
= T52 (SLP# assertion to clock shut off delay)
T
w
= T47 (Deep Sleep PLL lock latency)
T
x
= T54 (SLP# Hold Time)
T
y
= T55 (STPCLK# Hold Time)
T
z
= T56 (Input Signal Hold Time)