Intel 733 MHz RH80533NZ733128 Data Sheet

283654-003 Datasheet 

 

 

73 

The TESTLO[2:1] (Test input Low) signals are used during processor test and needs to be pulled 
to ground during normal operation.  

The THERMDA (Thermal Diode Anode) and THERMDC (Thermal Diode Cathode) signals 
connect to the anode and cathode of the on-die thermal diode. 

The TMS (Test Mode Select) signal is a JTAG support signal used by debug tools. 

The TRDY# (Target Ready) signal is asserted by the target to indicate that the target is ready to 
receive write or implicit write-back data transfer. TRDY# must be connected to the appropriate 
pins/balls on both agents on the system bus. 

The TRST# (Test Reset) signal resets the Test Access Port (TAP) logic. The mobile processors do 
not self-reset during power on; therefore, it is necessary to drive this signal low during power-on 
reset. 

The VID[4:0] (Voltage ID) pins/balls can be used to support automatic selection of power supply 
voltages. These pins/balls are not signals, they are either an open circuit or a short to V

SS

 on the 

processor substrate. The combination of opens and shorts encodes the voltage required by the 
processor. External to pull-ups are required to sense the encoded VID. VID[4:0] are needed to 
cleanly support voltage specification changes on mobile Intel Celeron processors. The voltage 
encoded by VID[4:0] is defined in Table 36. A “1” in this table refers to an open pin/ball and a “0” 
refers to a short to V

SS

. The power supply must provide the requested voltage or disable itself. 

Please note that in order to implement VID on the BGA2 package, some VID[4:0] balls may be 
depopulated. For the BGA2 package, a “1” in Table 36 implies that the corresponding VID ball is 
depopulated, while a “0” implies that the corresponding VID ball is not depopulated. 

But on the Micro-PGA2 package, VID[4:0] pins are not depopulated.