Intel T2500 BX80539T1500 User Manual

Datasheet

27

CMOS input signals are shown in 

. Legacy output FERR#, IERR# and other non-

AGTL+ signals (THERMTRIP# and PROCHOT#) utilize Open Drain output buffers. These 

signals do not have setup or hold time specifications in relation to BCLK[1:0]. However, 

all of the CMOS signals are required to be asserted for at least three BCLKs in order for 

the processor to recognize them. See 

 for the DC specifications for the 

CMOS signal groups.

 specifies absolute maximum and minimum ratings. Only within specified 

operation limits, can functionality and long-term reliability be expected. 

At condition outside functional operation condition limits, but within absolute maximum 

and minimum ratings, neither functionality nor long term reliability can be expected. If 

a device is returned to conditions within functional operation limits after having been 

subjected to conditions outside these limits, but within the absolute maximum and 

minimum ratings, the device may be functional, but with its lifetime degraded on 

exposure to conditions exceeding the functional operation condition limits.

At conditions exceeding absolute maximum and minimum ratings, neither functionality 

nor long term reliability can be expected. Moreover, if a device is subjected to these 

conditions for any length of time then, when returned to conditions within the 

functional operating condition limits, it will either not function or its reliability will be 

severely degraded.

Although the processor contains protective circuitry to resist damage from electro static 

discharge, precautions should always be taken to avoid high static voltages or electric 

fields.

NOTES:
1.

This rating applies to any processor pin.

2.

Contact Intel for storage requirements in excess of one year.

T

STORAGE

Processor Storage Temperature

 -40

 85

°C

2

V

CC

Any Processor Supply Voltage with Respect to V

SS

-0.3

1.6

V

1

V

inAGTL+

AGTL+ Buffer DC Input Voltage with Respect to V

SS

-0.3

1.6

V

1, 2

V

inAsynch_CMOS

CMOS Buffer DC iNput Voltage with Respect to V

SS

-0.3

1.6

V

1, 2