Intel T2500 BX80539T1500 User Manual

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Datasheet

and thermal attach and software application. The system designer is required to use 

the DTS to guarantee proper operation of the processor within its temperature 

operating specifications

Changes to the temperature can be detected via two programmable thresholds located 

in the processor MSRs. These thresholds have the capability of generating interrupts 

via the core's local APIC.

Overheat detection is performed by monitoring the processor temperature and 

temperature gradient. This feature is intended for graceful shut down before the 

THERMTRIP# is activated. If the processor’s TM1 or TM2 are triggered and the 

temperature remains high, an “Out Of Spec” status and sticky bit are latched in the 

status MSR register and generates thermal interrupt. 

An external signal, PROCHOT# (processor hot), is asserted when the processor die 

temperature has reached its maximum operating temperature. If the Intel Thermal 

Monitor 1 or Intel Thermal Monitor 2 is enabled (note that the Intel Thermal Monitor 1 

or Intel Thermal Monitor 2 must be enabled for the processor to be operating within 

specification), the TCC will be active when PROCHOT# is asserted. The processor can 

be configured to generate an interrupt upon the assertion or deassertion of 

PROCHOT#.

The processor implements a bi-directional PROCHOT# capability to allow system 

designs to protect various components from over-temperature situations. The 

PROCHOT# signal is bi-directional in that it can either signal when the processor has 

reached its maximum operating temperature or be driven from an external source to 

activate the TCC. The ability to activate the TCC via PROCHOT# can provide a means 

for thermal protection of system components.

In a dual core implementation, only a single PROCHOT# pin exists at a package level. 

When either core's thermal sensor trips, PROCHOT# signal will be driven by the 

processor package. If only TM1 is enabled, PROCHOT# will be asserted and only the 

core that is above TCC temperature trip point will have its core clocks modulated. If 

TM2 is enabled, then regardless of which core(s) are above TCC temperature trip point, 

both cores will enter the lowest programmed TM2 performance state.

It is important to note that Intel recommends both TM1 and TM2 be enabled.

When PROCHOT# is driven by an external agent, if only TM1 is enabled on both cores, 

then both processor cores will have their core clocks modulated.  If TM2 is enabled on 

both cores, then both processor core will enter the lowest programmed TM2 

performance state.

One application is the thermal protection of voltage regulators (VR). System designers 

can create a circuit to monitor the VR temperature and activate the TCC when the 

temperature limit of the VR is reached. By asserting PROCHOT# (pulled-low) and 

activating the TCC, the VR can cool down as a result of reduced processor power 

consumption. Bi-directional PROCHOT# can allow VR thermal designs to target 

maximum sustained current instead of maximum current. Systems should still provide 

proper cooling for the VR, and rely on bi-directional PROCHOT# only as a backup in 

case of system cooling failure. The system thermal design should allow the power 

delivery circuitry to operate within its temperature specification even while the 

processor is operating at its TDP. With a properly designed and characterized thermal 

solution, it is anticipated that bi-directional PROCHOT# would only be asserted for very