Intel 900 MHz KC80526NY900128 Data Sheet
Product codes
KC80526NY900128
R
Mobile Intel® Celeron® Processor Specification Update
19
NO.
BA2
PA2
MA2
BB0
PB0
MB0
BC0
PC0
MC0
BD0
PD0
FBD
O
FPDO
FBA1
FPA1
FBB1
FPB1
Plans
ERRATA
M80
X X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
NoFix
Page with PAT (Page Attribute
Table) Set to USWC (Uncacheable
Speculative Write Combine) While
Associated MTRR (Memory Type
Range Register) is UC
(Uncacheable) May Consolidate to
UC
Table) Set to USWC (Uncacheable
Speculative Write Combine) While
Associated MTRR (Memory Type
Range Register) is UC
(Uncacheable) May Consolidate to
UC
M81
X X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
NoFix
Under Certain Conditions LTR (Load
Task Register) Instruction May
Result in System Hang
Task Register) Instruction May
Result in System Hang
M82
X X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
NoFix
Loading from Memory Type USWC
(Uncacheable Speculative Write
Combine) May Get Its Data
Internally Forwarded from a
Previous Pending Store
(Uncacheable Speculative Write
Combine) May Get Its Data
Internally Forwarded from a
Previous Pending Store
M83
X X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
NoFix
FPU Operand Pointer May Not be
Cleared Following FINIT/FNINT
Cleared Following FINIT/FNINT
M84
X X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
NoFix
FSTP (Floating Point
Store) Instruction Under Certain
Conditions May Result In
Erroneously Setting a Valid Bit on an
FP (Floating Point) Stack Register
Store) Instruction Under Certain
Conditions May Result In
Erroneously Setting a Valid Bit on an
FP (Floating Point) Stack Register
M85
X X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
NoFix
Invalid Entries in Page-Directory-
Pointer-Table Register (PDPTR)
May Cause General Protection
(#GP) Exception if the Reserved Bits
are Set to One
Pointer-Table Register (PDPTR)
May Cause General Protection
(#GP) Exception if the Reserved Bits
are Set to One
M86
X X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
NoFix
Writing the Local Vector Table (LVT)
when an Interrupt is Pending May
Cause an Unexpected Interrupt
when an Interrupt is Pending May
Cause an Unexpected Interrupt
M87
X X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
NoFix
The Processor May Report an
Invalid TSS Fault Instead of a #GP
Fault
Invalid TSS Fault Instead of a #GP
Fault
M88
X X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
NoFix
A Write to an APIC Register
Sometimes May Appear to Have Not
Occurred
Sometimes May Appear to Have Not
Occurred
M89
X X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X NoFix
Using 2M/4M Pages When A20M#
Is Asserted May Result in Incorrect
Address Translations
Is Asserted May Result in Incorrect
Address Translations
M90 X X X X X X X X X X X X X X
X
X
X
NoFix
Values for LBR/BTS/BTM will be
Incorrect after an Exit from SMM
Incorrect after an Exit from SMM
M91 X X X X X X X X X X X X X X
X
X
X
NoFix
INIT Does Not Clear Global Entries
in the TLB
in the TLB
M92 X X X X X X X X X X X X X X
X
X
X
NoFix
REP MOVS/STOS Executing with
Fast Strings Enabled and Crossing
Page Boundaries with Inconsistent
Memory Types may use an Incorrect
Data Size or Lead to Memory-
Ordering Violations
Fast Strings Enabled and Crossing
Page Boundaries with Inconsistent
Memory Types may use an Incorrect
Data Size or Lead to Memory-
Ordering Violations
M93 X X X X X X X X X X X X X X
X
X
X
NoFix
The BS Flag in DR6 May be Set for
Non-Single-Step #DB Exception
Non-Single-Step #DB Exception