Intel 900 MHz KC80526NY900128 Data Sheet
Product codes
KC80526NY900128
R
Mobile Intel® Celeron® Processor Specification Update
25
Errata
M1.
WBINVD May Lock Write Out Buffer
Problem:
The FP Data Operand Pointer is the effective address of the operand associated with the last noncontrol
floating-point instruction executed by the machine. If an 80-bit floating-point access (load or store)
occurs in a 16-bit mode other than protected mode (in which case the access will produce a segment
limit violation), the memory access wraps a 64-Kbyte boundary, and the floating-point environment is
subsequently saved, the value contained in the FP Data Operand Pointer may be incorrect.
floating-point instruction executed by the machine. If an 80-bit floating-point access (load or store)
occurs in a 16-bit mode other than protected mode (in which case the access will produce a segment
limit violation), the memory access wraps a 64-Kbyte boundary, and the floating-point environment is
subsequently saved, the value contained in the FP Data Operand Pointer may be incorrect.
Implication:
A 32-bit operating system running 16-bit floating-point code may encounter this erratum, under the
following conditions:
following conditions:
• The operating system is using a segment greater than 64 Kbytes in size.
• An application is running in a 16-bit mode other than protected mode.
• An 80-bit floating-point load or store which wraps the 64-Kbyte boundary is executed.
• The operating system performs a floating-point environment store
(FSAVE/FNSAVE/FSTENV/FNSTENV) after the above memory access.
• The operating system uses the value contained in the FP Data Operand Pointer.
Wrapping an 80-bit floating-point load around a segment boundary in this way is not a normal
programming practice. Intel has not currently identified any software which exhibits this behavior.
programming practice. Intel has not currently identified any software which exhibits this behavior.
Workaround:
If the FP Data Operand Pointer is used in an OS which may run 16-bit floating-point code, care must be
taken to ensure that no 80-bit floating-point accesses are wrapped around a 64-Kbyte boundary.
taken to ensure that no 80-bit floating-point accesses are wrapped around a 64-Kbyte boundary.
Status:
For the steppings affected see the Summary of Changes at the beginning of this section.
M2.
Differences Exist in Debug Exception Reporting
Problem:
There exist some differences in the reporting of code and data breakpoint matches between that specified
by previous Intel processor specifications and the behavior of the Intel® Mobile Celeron® processor, as
described below:
by previous Intel processor specifications and the behavior of the Intel® Mobile Celeron® processor, as
described below:
Case 1: The first case is for a breakpoint set on a MOVSS or POPSS instruction, when the instruction
following it causes a debug register protection fault (DR7.gd is already set, enabling the fault). The
processor reports delayed data breakpoint matches from the MOVSS or POPSS instructions by setting
the matching DR6.bi bits, along with the debug register protection fault (DR6.bd). If additional
breakpoint faults are matched during the call of the debug fault handler, the processor sets the breakpoint
match bits (DR6.bi) to reflect the breakpoints matched by both the MOVSS or POPSS breakpoint and
the debug fault handler call. The Intel® Mobile Celeron® processor only sets DR6.bd in either situation,
and does not set any of the DR6.bi bits.
following it causes a debug register protection fault (DR7.gd is already set, enabling the fault). The
processor reports delayed data breakpoint matches from the MOVSS or POPSS instructions by setting
the matching DR6.bi bits, along with the debug register protection fault (DR6.bd). If additional
breakpoint faults are matched during the call of the debug fault handler, the processor sets the breakpoint
match bits (DR6.bi) to reflect the breakpoints matched by both the MOVSS or POPSS breakpoint and
the debug fault handler call. The Intel® Mobile Celeron® processor only sets DR6.bd in either situation,
and does not set any of the DR6.bi bits.