Intel 900 MHz KC80526NY900128 Data Sheet

Product codes

KC80526NY900128

Mobile Intel® Celeron® Processor Specification Update

Status:

For the steppings affected, see the Summary Tables of Changes

M93. The BS Flag in DR6 May be Set for Non-Single-Step #DB Exception

Problem:

DR6 BS (Single Step, bit 14) flag may be incorrectly set when the TF (Trap Flag, bit 8) of the EFLAGS
Register is set, and a #DB (Debug Exception) occurs due to one of the following:

• DR7 GD (General Detect, bit 13) being bit set;

• INT1 instruction;

• Code breakpoint

the DR6 BS (Single Step, bit 14) flag may be incorrectly set.

Implication:

The BS flag may be incorrectly set for non-single-step #DB exception.

Workaround:

None identified.

Status:

For the steppings affected, see the Summary Tables of Changes

M94.

Fault on ENTER Instruction May Result in Unexpected Values on Stack Frame

Problem:

The ENTER instruction is used to create a procedure stack frame. Due to this erratum, if execution of
the ENTER instruction results in a fault, the dynamic storage area of the resultant stack frame may
contain unexpected values (i.e. residual stack data as a result of processing the fault).

Implication:

Data in the created stack frame may be altered following a fault on the ENTER instruction. Please refer

to "Procedure Calls For Block-Structured Languages" in IA-32 Intel® Architecture Software
Developer’s Manual, Vol. 1, Basic Architecture, for information on the usage of the ENTER
instructions. This erratum is not expected to occur in ring 3. Faults are usually processed in ring 0 and
stack switch occurs when transferring to ring 0. Intel has not observed this erratum on any
commercially available software.

Workaround:

None identified.

Status:

For the steppings affected, see the Summary Tables of Changes