Intel 900 MHz KC80526NY900128 Data Sheet
Product codes
KC80526NY900128
R
Mobile Intel® Celeron® Processor Specification Update
61
6.
PDSLP is Deep Sleep power.
M2. SPECIFICATION CLARIFICATION WITH RESPECT TO TIME STAMP COUNTER
In the “Debugging and Performance Monitoring” section of the IA-32 Intel® Architecture Software
Developers Manual Software Developer’s Manual Volume 3: System Programming Guide, the Time
Stamp Counter definition has been updated to include support for the future processors. This change
will be incorporated in the next revision of the IA-32 Intel® Architecture Software Developers Manual
Software Developer’s Manual Volume 3: System Programming Guide.
Developers Manual Software Developer’s Manual Volume 3: System Programming Guide, the Time
Stamp Counter definition has been updated to include support for the future processors. This change
will be incorporated in the next revision of the IA-32 Intel® Architecture Software Developers Manual
Software Developer’s Manual Volume 3: System Programming Guide.
IA-32 Intel® Architecture Software Developers Manual Software Developer’s Manual Volume 3:
System Programming Guide Debugging and Performance Monitoring Section (Section 15.8, Section
15.10.9 and Section 15.10.9.3)
System Programming Guide Debugging and Performance Monitoring Section (Section 15.8, Section
15.10.9 and Section 15.10.9.3)
15.8 TIME-STAMP COUNTER
The IA-32 architecture (beginning with the Pentium processor) defines a time-stamp counter
mechanism that can be used to monitor and identify the relative time occurrence of processor events.
The counter’s architecture includes the following components:
mechanism that can be used to monitor and identify the relative time occurrence of processor events.
The counter’s architecture includes the following components:
•
TSC flag — A feature bit that indicates the availability of the time-stamp counter. The counter is
available in an IA-32 processor implementation if the function CPUID.1:EDX.TSC[bit 4] = 1.
•
IA32_TIME_STAMP_COUNTER MSR (called TSC MSR in P6 family and Pentium
processors) — The MSR used as the counter.
•
RDTSC instruction — An instruction used to read the time-stamp counter.
•
TSD flag — A control register flag is used to enable or disable the time-stamp counter (enabled if
CR4.TSD[bit 2] = 1).
The time-stamp counter (as implemented in the P6 family, Pentium, Pentium M, Pentium 4, and Intel
Xeon processors) is a 64-bit counter that is set to 0 following a RESET of the processor. Following a
RESET, the counter will increment even when the processor is halted by the HLT instruction or the
external STPCLK# pin. Note that the assertion of the external DPSLP# pin may cause the time-stamp
counter to stop.
Xeon processors) is a 64-bit counter that is set to 0 following a RESET of the processor. Following a
RESET, the counter will increment even when the processor is halted by the HLT instruction or the
external STPCLK# pin. Note that the assertion of the external DPSLP# pin may cause the time-stamp
counter to stop.
Members of the processor families increment the time-stamp counter differently:
•
For Pentium M processors (family [06H], models [09H, 0DH]); for Pentium 4 processors, Intel
Xeon processors (family [0FH], models [00H, 01H, or 02H]); and for P6 family processors: the
time-stamp counter increments with every internal processor clock cycle. The internal processor
clock cycle is determined by the current core-clock to bus-clock ratio. Intel SpeedStep®
technology transitions may also impact the processor clock.
time-stamp counter increments with every internal processor clock cycle. The internal processor
clock cycle is determined by the current core-clock to bus-clock ratio. Intel SpeedStep®
technology transitions may also impact the processor clock.
•
For Pentium 4 processors, Intel Xeon processors (family [0FH], models [03H and higher]): the
time-stamp counter increments at a constant rate. That rate may be set by the maximum core-clock
to bus-clock ratio of the processor or may be set by the frequency at which the processor is booted.
The specific processor configuration determines the behavior. Constant TSC behavior ensures that
the duration of each clock tick is uniform and supports the use of the TSC as a wall clock timer
even if the processor core changes frequency. This is the architectural behavior moving forward.
to bus-clock ratio of the processor or may be set by the frequency at which the processor is booted.
The specific processor configuration determines the behavior. Constant TSC behavior ensures that
the duration of each clock tick is uniform and supports the use of the TSC as a wall clock timer
even if the processor core changes frequency. This is the architectural behavior moving forward.