Intel U1300 LE80538UE0042M Data Sheet

16

  

 Specification 

Update 

The Intel Core Duo processor and Intel Core Solo processor on 65 nm process can be 

identified by the following register contents: 

  

0110 1110 

 

1. 

The family corresponds to bit [11:8] of the EDX register after RESET, bits [11:8] of the 

EAX register after the CPUID instruction is executed with a 1 in the EAX register, and 

the generation field of the Device ID register accessible through Boundary Scan. 

2. 

The family corresponds to bit [7:4] of the EDX register after RESET, bits [7:4] of the 

EAX register after the CPUID instruction is executed with a 1 in the EAX register, and 

the generation field of the Device ID register accessible through Boundary Scan. 

Cache and TLB descriptor parameters are provided in the EAX, EBX, ECX, and EDX 

registers after the CPUID instruction is executed with a 2 in the EAX register. Refer to 

the Intel® Processor Identification and the CPUID Instruction Application Note (AP-

485) for further information on the CPUID instruction.