Intel ULV 353 LE80536VC900512 Data Sheet
Product codes
LE80536VC900512
Mobile Intel
®
Celeron
®
Processor (0.18µ) in BGA2 and Micro-PGA2 Packages
283654-003 Datasheet
13
Table 2. Removed BGA1/µPGA1 Signals
Signals Purpose
EDGECTRLN
GTL+ output buffer control
BSEL
100/66 MHz processor system bus speed selection
2.2 Power
Management
2.2.1 Clock
Control
Architecture
The mobile Intel Celeron processor clock control architecture (Figure 2) has been optimized for
leading edge deep green desktop and mobile computer designs. The clock control architecture
consists of seven different clock states: Normal, Stop Grant, Auto Halt, Quick Start, HALT/Grant
Snoop, Sleep, and Deep Sleep states. The Auto Halt state provides a low-power clock state that
can be controlled through the software execution of the HLT instruction. The Quick Start state
provides a very low power and low exit latency clock state that can be used for hardware
controlled “idle” computer states. The Deep Sleep state provides an extremely low-power state
that can be used for “Power-On-Suspend” computer states, which is an alternative to shutting off
the processor’s power. Compared to the Pentium processor exit latency of 1 msec, the exit latency
of the Deep Sleep state has been reduced to 30
leading edge deep green desktop and mobile computer designs. The clock control architecture
consists of seven different clock states: Normal, Stop Grant, Auto Halt, Quick Start, HALT/Grant
Snoop, Sleep, and Deep Sleep states. The Auto Halt state provides a low-power clock state that
can be controlled through the software execution of the HLT instruction. The Quick Start state
provides a very low power and low exit latency clock state that can be used for hardware
controlled “idle” computer states. The Deep Sleep state provides an extremely low-power state
that can be used for “Power-On-Suspend” computer states, which is an alternative to shutting off
the processor’s power. Compared to the Pentium processor exit latency of 1 msec, the exit latency
of the Deep Sleep state has been reduced to 30
µ
sec in the mobile Intel Celeron processor. The
Stop Grant and Sleep states shown in Figure 2 are intended for use in “Deep Green” desktop and
server systems — not in mobile systems. Performing state transitions not shown in Figure 2 is
neither recommended nor supported.
server systems — not in mobile systems. Performing state transitions not shown in Figure 2 is
neither recommended nor supported.
The Stop Grant and Quick Start clock states are mutually exclusive, i.e., a strapping option on
signal A15# chooses which state is entered when the STPCLK# signal is asserted. The Quick Start
state is enabled by strapping the A15# signal to ground at Reset; otherwise, asserting the
STPCLK# signal puts the processor into the Stop Grant state. The Stop Grant state has a higher
power level than the Quick Start state and is designed for Symmetric Multi-Processing (SMP)
platforms. The Quick Start state has a much lower power level, but it can only be used in
uniprocessor platforms. Table 3 provides clock state characteristics, which are described in detail
in the following sections.
signal A15# chooses which state is entered when the STPCLK# signal is asserted. The Quick Start
state is enabled by strapping the A15# signal to ground at Reset; otherwise, asserting the
STPCLK# signal puts the processor into the Stop Grant state. The Stop Grant state has a higher
power level than the Quick Start state and is designed for Symmetric Multi-Processing (SMP)
platforms. The Quick Start state has a much lower power level, but it can only be used in
uniprocessor platforms. Table 3 provides clock state characteristics, which are described in detail
in the following sections.
2.2.2 Normal
State
The Normal state of the processor is the normal operating mode where the processor’s core clock
is running and the processor is actively executing instructions.
is running and the processor is actively executing instructions.
2.2.3
Auto Halt State
This is a low-power mode entered by the processor through the execution of the HLT instruction.
The power level of this mode is similar to the Stop Grant state. A transition to the Normal state is
made by a halt break event (one of the following signals going active: NMI, INTR, BINIT#,
INIT#, RESET#, FLUSH#, or SMI#).
The power level of this mode is similar to the Stop Grant state. A transition to the Normal state is
made by a halt break event (one of the following signals going active: NMI, INTR, BINIT#,
INIT#, RESET#, FLUSH#, or SMI#).
Asserting the STPCLK# signal while in the Auto Halt state will cause the processor to transition
to the Stop Grant or Quick Start state, where a Stop Grant Acknowledge bus cycle will be issued.
Deasserting STPCLK# will cause the processor to return to the Auto Halt state without issuing a
new Halt bus cycle.
to the Stop Grant or Quick Start state, where a Stop Grant Acknowledge bus cycle will be issued.
Deasserting STPCLK# will cause the processor to return to the Auto Halt state without issuing a
new Halt bus cycle.